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Searched refs:MLXSW_ITEM32 (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/net/ethernet/mellanox/mlxsw/
A Dcmd.h241 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1);
252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8);
272 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8);
277 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8);
644 MLXSW_ITEM32(cmd_mbox, config_profile,
753 MLXSW_ITEM32(cmd_mbox, config_profile,
759 MLXSW_ITEM32(cmd_mbox, config_profile,
936 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8);
1083 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1);
1090 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1);
[all …]
A Dreg.h47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
615 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
901 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
1669 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
2234 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
[all …]
A Dpci_hw.h77 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
89 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
94 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
146 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
194 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
195 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
201 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
202 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
209 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
216 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
[all …]
A Dcore_acl_flex_actions.c26 MLXSW_ITEM32(afa, set, type, 0xA0, 28, 4);
38 MLXSW_ITEM32(afa, set, goto_g, 0xA4, 29, 1);
61 MLXSW_ITEM32(afa, all, action_type, 0x00, 24, 6);
1107 MLXSW_ITEM32(afa, vlan, vid, 0x04, 0, 12);
1121 MLXSW_ITEM32(afa, vlan, pcp, 0x08, 8, 3);
1477 MLXSW_ITEM32(afa, qos, ecn, 0x04, 24, 2);
1498 MLXSW_ITEM32(afa, qos, dscp, 0x04, 0, 6);
1722 MLXSW_ITEM32(afa, polcnt, c_p, 0x00, 31, 1);
1747 MLXSW_ITEM32(afa, polcnt, pid, 0x08, 0, 14);
1864 MLXSW_ITEM32(afa, virfwd, fid, 0x08, 0, 16);
[all …]
A Dcore.c247 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4);
253 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5);
259 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11);
267 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1);
284 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7);
294 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1);
303 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7);
308 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8);
338 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5);
343 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11);
[all …]
A Dspectrum.c110 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
117 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
122 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
127 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
133 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
138 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
144 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
149 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
159 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
166 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
[all …]
A Ditem.h352 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ macro

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