Searched refs:MMC_TIMING_UHS_DDR50 (Results 1 – 25 of 34) sorted by relevance
12
658 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sdcardclk_set_phase()727 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sampleclk_set_phase()787 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sdcardclk_set_phase()854 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sampleclk_set_phase()926 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_execute_tuning()1123 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, in arasan_dt_parse_clk_phases()
268 case MMC_TIMING_UHS_DDR50: in pxav3_set_uhs_signaling()281 uhs == MMC_TIMING_UHS_DDR50) { in pxav3_set_uhs_signaling()
39 ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798cv200_set_ios()
214 else if ((timing == MMC_TIMING_UHS_DDR50) || in xenon_set_uhs_signaling()369 if (host->timing == MMC_TIMING_UHS_DDR50 || in xenon_execute_tuning()
1028 case MMC_TIMING_UHS_DDR50: in sd_set_timing()1109 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()1329 case MMC_TIMING_UHS_DDR50: in sdmmc_execute_tuning()1344 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in sdmmc_execute_tuning()
620 case MMC_TIMING_UHS_DDR50: in xenon_emmc_phy_set()754 case MMC_TIMING_UHS_DDR50: in xenon_hs_delay_adj()
89 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_brcmstb_set_uhs_signaling()
284 case MMC_TIMING_UHS_DDR50: in arasan_select_phy_clock()
291 case MMC_TIMING_UHS_DDR50: in sdhci_st_set_uhs_signaling()
1018 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()1128 case MMC_TIMING_UHS_DDR50: in esdhc_change_pinstate()1253 case MMC_TIMING_UHS_DDR50: in esdhc_set_uhs_signaling()
149 else if ((timing == MMC_TIMING_UHS_DDR50) || in dwcmshc_set_uhs_signaling()
750 if (ios->timing != MMC_TIMING_UHS_DDR50) { in usdhi6_clk_set()853 if (ios->timing == MMC_TIMING_UHS_DDR50) in usdhi6_set_ios()860 mode = ios->timing == MMC_TIMING_UHS_DDR50; in usdhi6_set_ios()
320 case MMC_TIMING_UHS_DDR50: in dw_mci_exynos_set_ios()
200 host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) in mmci_sdmmc_set_clkreg()
831 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()1154 pinctrl_state[MMC_TIMING_UHS_DDR50] = state; in sdhci_omap_config_iodelay_pinctrl_state()
740 if (ios->timing != MMC_TIMING_UHS_DDR50 && in sunxi_mmc_clk_set_phase()890 if (ios->timing == MMC_TIMING_UHS_DDR50 || in sunxi_mmc_set_clk()
1061 case MMC_TIMING_UHS_DDR50: in sd_set_timing()1127 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
523 if (ios->timing == MMC_TIMING_UHS_DDR50) { in owl_mmc_set_ios()
344 case MMC_TIMING_UHS_DDR50: in sdhci_sprd_set_uhs_signaling()
126 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
1842 case MMC_TIMING_UHS_DDR50: in sdhci_get_preset_value()2248 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_uhs_signaling()2323 ios->timing == MMC_TIMING_UHS_DDR50 || in sdhci_set_ios()2388 (ios->timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_ios()2862 case MMC_TIMING_UHS_DDR50: in sdhci_execute_tuning()
60 #define MMC_TIMING_UHS_DDR50 7 macro607 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; in mmc_card_uhs()
141 case MMC_TIMING_UHS_DDR50: in mmc_ios_show()
489 timing = MMC_TIMING_UHS_DDR50; in sd_set_bus_speed_mode()661 card->host->ios.timing == MMC_TIMING_UHS_DDR50 || in mmc_sd_init_uhs_card()672 if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) { in mmc_sd_init_uhs_card()
257 &map->phase[MMC_TIMING_UHS_DDR50]); in mmc_of_parse_clk_phase()
Completed in 54 milliseconds