Home
last modified time | relevance | path

Searched refs:MPLL_DQ_FUNC_CNTL (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/radeon/
A Drv740d.h63 #define MPLL_DQ_FUNC_CNTL 0x62c macro
A Drv740_dpm.c303 RREG32(MPLL_DQ_FUNC_CNTL); in rv740_read_clock_registers()
A Drv770d.h136 #define MPLL_DQ_FUNC_CNTL 0x62c macro
A Dnid.h578 #define MPLL_DQ_FUNC_CNTL 0x62c macro
A Dsid.h626 #define MPLL_DQ_FUNC_CNTL 0x2bc4 macro
A Dcikd.h749 #define MPLL_DQ_FUNC_CNTL 0x2bc4 macro
A Devergreend.h116 #define MPLL_DQ_FUNC_CNTL 0x62c macro
A Drv770_dpm.c1537 RREG32(MPLL_DQ_FUNC_CNTL); in rv770_read_clock_registers()
A Dni_dpm.c1191 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ni_read_clock_registers()
A Dci_dpm.c1852 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
A Dsi_dpm.c3561 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Diceland_smumgr.c1090 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); in iceland_calculate_mclk_params()
1092 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
A Dci_smumgr.c1063 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); in ci_calculate_mclk_params()
1065 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
A Dtonga_smumgr.c840 MPLL_DQ_FUNC_CNTL, YCLK_SEL, in tonga_calculate_mclk_params()
843 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, in tonga_calculate_mclk_params()
/linux/drivers/gpu/drm/amd/amdgpu/
A Dsid.h627 #define MPLL_DQ_FUNC_CNTL 0xAF1 macro
/linux/drivers/gpu/drm/amd/pm/powerplay/
A Dsi_dpm.c4020 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()

Completed in 130 milliseconds