1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3 
4 #ifndef __MT7915_MAC_H
5 #define __MT7915_MAC_H
6 
7 #define MT_CT_PARSE_LEN			72
8 #define MT_CT_DMA_BUF_NUM		2
9 
10 #define MT_RXD0_LENGTH			GENMASK(15, 0)
11 #define MT_RXD0_PKT_TYPE		GENMASK(31, 27)
12 
13 #define MT_RXD0_NORMAL_ETH_TYPE_OFS	GENMASK(22, 16)
14 #define MT_RXD0_NORMAL_IP_SUM		BIT(23)
15 #define MT_RXD0_NORMAL_UDP_TCP_SUM	BIT(24)
16 
17 enum rx_pkt_type {
18 	PKT_TYPE_TXS,
19 	PKT_TYPE_TXRXV,
20 	PKT_TYPE_NORMAL,
21 	PKT_TYPE_RX_DUP_RFB,
22 	PKT_TYPE_RX_TMR,
23 	PKT_TYPE_RETRIEVE,
24 	PKT_TYPE_TXRX_NOTIFY,
25 	PKT_TYPE_RX_EVENT,
26 };
27 
28 /* RXD DW1 */
29 #define MT_RXD1_NORMAL_WLAN_IDX		GENMASK(9, 0)
30 #define MT_RXD1_NORMAL_GROUP_1		BIT(11)
31 #define MT_RXD1_NORMAL_GROUP_2		BIT(12)
32 #define MT_RXD1_NORMAL_GROUP_3		BIT(13)
33 #define MT_RXD1_NORMAL_GROUP_4		BIT(14)
34 #define MT_RXD1_NORMAL_GROUP_5		BIT(15)
35 #define MT_RXD1_NORMAL_SEC_MODE		GENMASK(20, 16)
36 #define MT_RXD1_NORMAL_KEY_ID		GENMASK(22, 21)
37 #define MT_RXD1_NORMAL_CM		BIT(23)
38 #define MT_RXD1_NORMAL_CLM		BIT(24)
39 #define MT_RXD1_NORMAL_ICV_ERR		BIT(25)
40 #define MT_RXD1_NORMAL_TKIP_MIC_ERR	BIT(26)
41 #define MT_RXD1_NORMAL_FCS_ERR		BIT(27)
42 #define MT_RXD1_NORMAL_BAND_IDX		BIT(28)
43 #define MT_RXD1_NORMAL_SPP_EN		BIT(29)
44 #define MT_RXD1_NORMAL_ADD_OM		BIT(30)
45 #define MT_RXD1_NORMAL_SEC_DONE		BIT(31)
46 
47 /* RXD DW2 */
48 #define MT_RXD2_NORMAL_BSSID		GENMASK(5, 0)
49 #define MT_RXD2_NORMAL_CO_ANT		BIT(6)
50 #define MT_RXD2_NORMAL_BF_CQI		BIT(7)
51 #define MT_RXD2_NORMAL_MAC_HDR_LEN	GENMASK(12, 8)
52 #define MT_RXD2_NORMAL_HDR_TRANS	BIT(13)
53 #define MT_RXD2_NORMAL_HDR_OFFSET	GENMASK(15, 14)
54 #define MT_RXD2_NORMAL_TID		GENMASK(19, 16)
55 #define MT_RXD2_NORMAL_MU_BAR		BIT(21)
56 #define MT_RXD2_NORMAL_SW_BIT		BIT(22)
57 #define MT_RXD2_NORMAL_AMSDU_ERR	BIT(23)
58 #define MT_RXD2_NORMAL_MAX_LEN_ERROR	BIT(24)
59 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR	BIT(25)
60 #define MT_RXD2_NORMAL_INT_FRAME	BIT(26)
61 #define MT_RXD2_NORMAL_FRAG		BIT(27)
62 #define MT_RXD2_NORMAL_NULL_FRAME	BIT(28)
63 #define MT_RXD2_NORMAL_NDATA		BIT(29)
64 #define MT_RXD2_NORMAL_NON_AMPDU	BIT(30)
65 #define MT_RXD2_NORMAL_BF_REPORT	BIT(31)
66 
67 /* RXD DW3 */
68 #define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)
69 #define MT_RXD3_NORMAL_CH_FREQ		GENMASK(15, 8)
70 #define MT_RXD3_NORMAL_ADDR_TYPE	GENMASK(17, 16)
71 #define MT_RXD3_NORMAL_U2M		BIT(0)
72 #define MT_RXD3_NORMAL_HTC_VLD		BIT(0)
73 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS	BIT(19)
74 #define MT_RXD3_NORMAL_BEACON_MC	BIT(20)
75 #define MT_RXD3_NORMAL_BEACON_UC	BIT(21)
76 #define MT_RXD3_NORMAL_AMSDU		BIT(22)
77 #define MT_RXD3_NORMAL_MESH		BIT(23)
78 #define MT_RXD3_NORMAL_MHCP		BIT(24)
79 #define MT_RXD3_NORMAL_NO_INFO_WB	BIT(25)
80 #define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS	BIT(26)
81 #define MT_RXD3_NORMAL_POWER_SAVE_STAT	BIT(27)
82 #define MT_RXD3_NORMAL_MORE		BIT(28)
83 #define MT_RXD3_NORMAL_UNWANT		BIT(29)
84 #define MT_RXD3_NORMAL_RX_DROP		BIT(30)
85 #define MT_RXD3_NORMAL_VLAN2ETH		BIT(31)
86 
87 /* RXD DW4 */
88 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT	GENMASK(1, 0)
89 #define MT_RXD4_FIRST_AMSDU_FRAME	GENMASK(1, 0)
90 #define MT_RXD4_MID_AMSDU_FRAME		BIT(1)
91 #define MT_RXD4_LAST_AMSDU_FRAME	BIT(0)
92 
93 #define MT_RXD4_NORMAL_PATTERN_DROP	BIT(9)
94 #define MT_RXD4_NORMAL_CLS		BIT(10)
95 #define MT_RXD4_NORMAL_OFLD		GENMASK(12, 11)
96 #define MT_RXD4_NORMAL_MAGIC_PKT	BIT(13)
97 #define MT_RXD4_NORMAL_WOL		GENMASK(18, 14)
98 #define MT_RXD4_NORMAL_CLS_BITMAP	GENMASK(28, 19)
99 #define MT_RXD3_NORMAL_PF_MODE		BIT(29)
100 #define MT_RXD3_NORMAL_PF_STS		GENMASK(31, 30)
101 
102 #define MT_RXV_HDR_BAND_IDX		BIT(24)
103 
104 /* RXD GROUP4 */
105 #define MT_RXD6_FRAME_CONTROL		GENMASK(15, 0)
106 #define MT_RXD6_TA_LO			GENMASK(31, 16)
107 
108 #define MT_RXD7_TA_HI			GENMASK(31, 0)
109 
110 #define MT_RXD8_SEQ_CTRL		GENMASK(15, 0)
111 #define MT_RXD8_QOS_CTL			GENMASK(31, 16)
112 
113 #define MT_RXD9_HT_CONTROL		GENMASK(31, 0)
114 
115 /* P-RXV */
116 #define MT_PRXV_TX_RATE			GENMASK(6, 0)
117 #define MT_PRXV_TX_DCM			BIT(4)
118 #define MT_PRXV_TX_ER_SU_106T		BIT(5)
119 #define MT_PRXV_NSTS			GENMASK(9, 7)
120 #define MT_PRXV_TXBF			BIT(10)
121 #define MT_PRXV_HT_AD_CODE		BIT(11)
122 #define MT_PRXV_HE_RU_ALLOC_L		GENMASK(31, 28)
123 #define MT_PRXV_HE_RU_ALLOC_H		GENMASK(3, 0)
124 #define MT_PRXV_RCPI3			GENMASK(31, 24)
125 #define MT_PRXV_RCPI2			GENMASK(23, 16)
126 #define MT_PRXV_RCPI1			GENMASK(15, 8)
127 #define MT_PRXV_RCPI0			GENMASK(7, 0)
128 
129 /* C-RXV */
130 #define MT_CRXV_HT_STBC			GENMASK(1, 0)
131 #define MT_CRXV_TX_MODE			GENMASK(7, 4)
132 #define MT_CRXV_FRAME_MODE		GENMASK(10, 8)
133 #define MT_CRXV_HT_SHORT_GI		GENMASK(14, 13)
134 #define MT_CRXV_HE_LTF_SIZE		GENMASK(18, 17)
135 #define MT_CRXV_HE_LDPC_EXT_SYM		BIT(20)
136 #define MT_CRXV_HE_PE_DISAMBIG		BIT(23)
137 #define MT_CRXV_HE_NUM_USER		GENMASK(30, 24)
138 #define MT_CRXV_HE_UPLINK		BIT(31)
139 #define MT_CRXV_HE_RU0			GENMASK(7, 0)
140 #define MT_CRXV_HE_RU1			GENMASK(15, 8)
141 #define MT_CRXV_HE_RU2			GENMASK(23, 16)
142 #define MT_CRXV_HE_RU3			GENMASK(31, 24)
143 
144 #define MT_CRXV_HE_MU_AID		GENMASK(30, 20)
145 
146 #define MT_CRXV_HE_SR_MASK		GENMASK(11, 8)
147 #define MT_CRXV_HE_SR1_MASK		GENMASK(16, 12)
148 #define MT_CRXV_HE_SR2_MASK             GENMASK(20, 17)
149 #define MT_CRXV_HE_SR3_MASK             GENMASK(24, 21)
150 
151 #define MT_CRXV_HE_BSS_COLOR		GENMASK(5, 0)
152 #define MT_CRXV_HE_TXOP_DUR		GENMASK(12, 6)
153 #define MT_CRXV_HE_BEAM_CHNG		BIT(13)
154 #define MT_CRXV_HE_DOPPLER		BIT(16)
155 
156 #define MT_CRXV_SNR		GENMASK(18, 13)
157 #define MT_CRXV_FOE_LO		GENMASK(31, 19)
158 #define MT_CRXV_FOE_HI		GENMASK(6, 0)
159 #define MT_CRXV_FOE_SHIFT	13
160 
161 enum tx_header_format {
162 	MT_HDR_FORMAT_802_3,
163 	MT_HDR_FORMAT_CMD,
164 	MT_HDR_FORMAT_802_11,
165 	MT_HDR_FORMAT_802_11_EXT,
166 };
167 
168 enum tx_pkt_type {
169 	MT_TX_TYPE_CT,
170 	MT_TX_TYPE_SF,
171 	MT_TX_TYPE_CMD,
172 	MT_TX_TYPE_FW,
173 };
174 
175 enum tx_port_idx {
176 	MT_TX_PORT_IDX_LMAC,
177 	MT_TX_PORT_IDX_MCU
178 };
179 
180 enum tx_mcu_port_q_idx {
181 	MT_TX_MCU_PORT_RX_Q0 = 0x20,
182 	MT_TX_MCU_PORT_RX_Q1,
183 	MT_TX_MCU_PORT_RX_Q2,
184 	MT_TX_MCU_PORT_RX_Q3,
185 	MT_TX_MCU_PORT_RX_FWDL = 0x3e
186 };
187 
188 #define MT_CT_INFO_APPLY_TXD		BIT(0)
189 #define MT_CT_INFO_COPY_HOST_TXD_ALL	BIT(1)
190 #define MT_CT_INFO_MGMT_FRAME		BIT(2)
191 #define MT_CT_INFO_NONE_CIPHER_FRAME	BIT(3)
192 #define MT_CT_INFO_HSR2_TX		BIT(4)
193 #define MT_CT_INFO_FROM_HOST		BIT(7)
194 
195 #define MT_TXD_SIZE			(8 * 4)
196 
197 #define MT_TXD0_Q_IDX			GENMASK(31, 25)
198 #define MT_TXD0_PKT_FMT			GENMASK(24, 23)
199 #define MT_TXD0_ETH_TYPE_OFFSET		GENMASK(22, 16)
200 #define MT_TXD0_TX_BYTES		GENMASK(15, 0)
201 
202 #define MT_TXD1_LONG_FORMAT		BIT(31)
203 #define MT_TXD1_TGID			BIT(30)
204 #define MT_TXD1_OWN_MAC			GENMASK(29, 24)
205 #define MT_TXD1_AMSDU			BIT(23)
206 #define MT_TXD1_TID			GENMASK(22, 20)
207 #define MT_TXD1_HDR_PAD			GENMASK(19, 18)
208 #define MT_TXD1_HDR_FORMAT		GENMASK(17, 16)
209 #define MT_TXD1_HDR_INFO		GENMASK(15, 11)
210 #define MT_TXD1_ETH_802_3		BIT(15)
211 #define MT_TXD1_VTA			BIT(10)
212 #define MT_TXD1_WLAN_IDX		GENMASK(9, 0)
213 
214 #define MT_TXD2_FIX_RATE		BIT(31)
215 #define MT_TXD2_FIXED_RATE		BIT(30)
216 #define MT_TXD2_POWER_OFFSET		GENMASK(29, 24)
217 #define MT_TXD2_MAX_TX_TIME		GENMASK(23, 16)
218 #define MT_TXD2_FRAG			GENMASK(15, 14)
219 #define MT_TXD2_HTC_VLD			BIT(13)
220 #define MT_TXD2_DURATION		BIT(12)
221 #define MT_TXD2_BIP			BIT(11)
222 #define MT_TXD2_MULTICAST		BIT(10)
223 #define MT_TXD2_RTS			BIT(9)
224 #define MT_TXD2_SOUNDING		BIT(8)
225 #define MT_TXD2_NDPA			BIT(7)
226 #define MT_TXD2_NDP			BIT(6)
227 #define MT_TXD2_FRAME_TYPE		GENMASK(5, 4)
228 #define MT_TXD2_SUB_TYPE		GENMASK(3, 0)
229 
230 #define MT_TXD3_SN_VALID		BIT(31)
231 #define MT_TXD3_PN_VALID		BIT(30)
232 #define MT_TXD3_SW_POWER_MGMT		BIT(29)
233 #define MT_TXD3_BA_DISABLE		BIT(28)
234 #define MT_TXD3_SEQ			GENMASK(27, 16)
235 #define MT_TXD3_REM_TX_COUNT		GENMASK(15, 11)
236 #define MT_TXD3_TX_COUNT		GENMASK(10, 6)
237 #define MT_TXD3_TIMING_MEASURE		BIT(5)
238 #define MT_TXD3_DAS			BIT(4)
239 #define MT_TXD3_EEOSP			BIT(3)
240 #define MT_TXD3_EMRD			BIT(2)
241 #define MT_TXD3_PROTECT_FRAME		BIT(1)
242 #define MT_TXD3_NO_ACK			BIT(0)
243 
244 #define MT_TXD4_PN_LOW			GENMASK(31, 0)
245 
246 #define MT_TXD5_PN_HIGH			GENMASK(31, 16)
247 #define MT_TXD5_MD			BIT(15)
248 #define MT_TXD5_ADD_BA			BIT(14)
249 #define MT_TXD5_TX_STATUS_HOST		BIT(10)
250 #define MT_TXD5_TX_STATUS_MCU		BIT(9)
251 #define MT_TXD5_TX_STATUS_FMT		BIT(8)
252 #define MT_TXD5_PID			GENMASK(7, 0)
253 
254 #define MT_TXD6_TX_IBF			BIT(31)
255 #define MT_TXD6_TX_EBF			BIT(30)
256 #define MT_TXD6_TX_RATE			GENMASK(29, 16)
257 #define MT_TXD6_SGI			GENMASK(15, 14)
258 #define MT_TXD6_HELTF			GENMASK(13, 12)
259 #define MT_TXD6_LDPC			BIT(11)
260 #define MT_TXD6_SPE_ID_IDX		BIT(10)
261 #define MT_TXD6_ANT_ID			GENMASK(7, 4)
262 #define MT_TXD6_DYN_BW			BIT(3)
263 #define MT_TXD6_FIXED_BW		BIT(2)
264 #define MT_TXD6_BW			GENMASK(1, 0)
265 
266 #define MT_TXD7_TXD_LEN			GENMASK(31, 30)
267 #define MT_TXD7_UDP_TCP_SUM		BIT(29)
268 #define MT_TXD7_IP_SUM			BIT(28)
269 
270 #define MT_TXD7_TYPE			GENMASK(21, 20)
271 #define MT_TXD7_SUB_TYPE		GENMASK(19, 16)
272 
273 #define MT_TXD7_PSE_FID			GENMASK(27, 16)
274 #define MT_TXD7_SPE_IDX			GENMASK(15, 11)
275 #define MT_TXD7_HW_AMSDU		BIT(10)
276 #define MT_TXD7_TX_TIME			GENMASK(9, 0)
277 
278 #define MT_TX_RATE_STBC			BIT(13)
279 #define MT_TX_RATE_NSS			GENMASK(12, 10)
280 #define MT_TX_RATE_MODE			GENMASK(9, 6)
281 #define MT_TX_RATE_SU_EXT_TONE		BIT(5)
282 #define MT_TX_RATE_DCM			BIT(4)
283 /* VHT/HE only use bits 0-3 */
284 #define MT_TX_RATE_IDX			GENMASK(5, 0)
285 
286 #define MT_TXP_MAX_BUF_NUM		6
287 
288 struct mt7915_txp {
289 	__le16 flags;
290 	__le16 token;
291 	u8 bss_idx;
292 	__le16 rept_wds_wcid;
293 	u8 nbuf;
294 	__le32 buf[MT_TXP_MAX_BUF_NUM];
295 	__le16 len[MT_TXP_MAX_BUF_NUM];
296 } __packed __aligned(4);
297 
298 struct mt7915_tx_free {
299 	__le16 rx_byte_cnt;
300 	__le16 ctrl;
301 	u8 txd_cnt;
302 	u8 rsv[3];
303 	__le32 info[];
304 } __packed __aligned(4);
305 
306 #define MT_TX_FREE_MSDU_CNT		GENMASK(9, 0)
307 #define MT_TX_FREE_WLAN_ID		GENMASK(23, 14)
308 #define MT_TX_FREE_LATENCY		GENMASK(12, 0)
309 /* 0: success, others: dropped */
310 #define MT_TX_FREE_STATUS		GENMASK(14, 13)
311 #define MT_TX_FREE_MSDU_ID		GENMASK(30, 16)
312 #define MT_TX_FREE_PAIR			BIT(31)
313 /* will support this field in further revision */
314 #define MT_TX_FREE_RATE			GENMASK(13, 0)
315 
316 #define MT_TXS0_FIXED_RATE		BIT(31)
317 #define MT_TXS0_BW			GENMASK(30, 29)
318 #define MT_TXS0_TID			GENMASK(28, 26)
319 #define MT_TXS0_AMPDU			BIT(25)
320 #define MT_TXS0_TXS_FORMAT		GENMASK(24, 23)
321 #define MT_TXS0_BA_ERROR		BIT(22)
322 #define MT_TXS0_PS_FLAG			BIT(21)
323 #define MT_TXS0_TXOP_TIMEOUT		BIT(20)
324 #define MT_TXS0_BIP_ERROR		BIT(19)
325 
326 #define MT_TXS0_QUEUE_TIMEOUT		BIT(18)
327 #define MT_TXS0_RTS_TIMEOUT		BIT(17)
328 #define MT_TXS0_ACK_TIMEOUT		BIT(16)
329 #define MT_TXS0_ACK_ERROR_MASK		GENMASK(18, 16)
330 
331 #define MT_TXS0_TX_STATUS_HOST		BIT(15)
332 #define MT_TXS0_TX_STATUS_MCU		BIT(14)
333 #define MT_TXS0_TX_RATE			GENMASK(13, 0)
334 
335 #define MT_TXS1_SEQNO			GENMASK(31, 20)
336 #define MT_TXS1_RESP_RATE		GENMASK(19, 16)
337 #define MT_TXS1_RXV_SEQNO		GENMASK(15, 8)
338 #define MT_TXS1_TX_POWER_DBM		GENMASK(7, 0)
339 
340 #define MT_TXS2_BF_STATUS		GENMASK(31, 30)
341 #define MT_TXS2_LAST_TX_RATE		GENMASK(29, 27)
342 #define MT_TXS2_SHARED_ANTENNA		BIT(26)
343 #define MT_TXS2_WCID			GENMASK(25, 16)
344 #define MT_TXS2_TX_DELAY		GENMASK(15, 0)
345 
346 #define MT_TXS3_PID			GENMASK(31, 24)
347 #define MT_TXS3_ANT_ID			GENMASK(23, 0)
348 
349 #define MT_TXS4_TIMESTAMP		GENMASK(31, 0)
350 
351 #define MT_TXS5_F0_FINAL_MPDU		BIT(31)
352 #define MT_TXS5_F0_QOS			BIT(30)
353 #define MT_TXS5_F0_TX_COUNT		GENMASK(29, 25)
354 #define MT_TXS5_F0_FRONT_TIME		GENMASK(24, 0)
355 #define MT_TXS5_F1_MPDU_TX_COUNT	GENMASK(31, 24)
356 #define MT_TXS5_F1_MPDU_TX_BYTES	GENMASK(23, 0)
357 
358 #define MT_TXS6_F0_NOISE_3		GENMASK(31, 24)
359 #define MT_TXS6_F0_NOISE_2		GENMASK(23, 16)
360 #define MT_TXS6_F0_NOISE_1		GENMASK(15, 8)
361 #define MT_TXS6_F0_NOISE_0		GENMASK(7, 0)
362 #define MT_TXS6_F1_MPDU_FAIL_COUNT	GENMASK(31, 24)
363 #define MT_TXS6_F1_MPDU_FAIL_BYTES	GENMASK(23, 0)
364 
365 #define MT_TXS7_F0_RCPI_3		GENMASK(31, 24)
366 #define MT_TXS7_F0_RCPI_2		GENMASK(23, 16)
367 #define MT_TXS7_F0_RCPI_1		GENMASK(15, 8)
368 #define MT_TXS7_F0_RCPI_0		GENMASK(7, 0)
369 #define MT_TXS7_F1_MPDU_RETRY_COUNT	GENMASK(31, 24)
370 #define MT_TXS7_F1_MPDU_RETRY_BYTES	GENMASK(23, 0)
371 
372 struct mt7915_dfs_pulse {
373 	u32 max_width;		/* us */
374 	int max_pwr;		/* dbm */
375 	int min_pwr;		/* dbm */
376 	u32 min_stgr_pri;	/* us */
377 	u32 max_stgr_pri;	/* us */
378 	u32 min_cr_pri;		/* us */
379 	u32 max_cr_pri;		/* us */
380 };
381 
382 struct mt7915_dfs_pattern {
383 	u8 enb;
384 	u8 stgr;
385 	u8 min_crpn;
386 	u8 max_crpn;
387 	u8 min_crpr;
388 	u8 min_pw;
389 	u32 min_pri;
390 	u32 max_pri;
391 	u8 max_pw;
392 	u8 min_crbn;
393 	u8 max_crbn;
394 	u8 min_stgpn;
395 	u8 max_stgpn;
396 	u8 min_stgpr;
397 	u8 rsv[2];
398 	u32 min_stgpr_diff;
399 } __packed;
400 
401 struct mt7915_dfs_radar_spec {
402 	struct mt7915_dfs_pulse pulse_th;
403 	struct mt7915_dfs_pattern radar_pattern[16];
404 };
405 
406 static inline struct mt7915_txp *
mt7915_txwi_to_txp(struct mt76_dev * dev,struct mt76_txwi_cache * t)407 mt7915_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
408 {
409 	u8 *txwi;
410 
411 	if (!t)
412 		return NULL;
413 
414 	txwi = mt76_get_txwi_ptr(dev, t);
415 
416 	return (struct mt7915_txp *)(txwi + MT_TXD_SIZE);
417 }
418 
419 #endif
420