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Searched refs:MUX_M0 (Results 1 – 5 of 5) sorted by relevance

/linux/arch/arm64/boot/dts/hisilicon/
A Dhikey-pinctrl.dtsi22 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
28 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
29 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
30 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
31 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
32 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
33 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
34 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
35 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
36 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */
[all …]
A Dhikey960-pinctrl.dtsi39 0x044 MUX_M0 /* CSI0_PWD_N */
45 0x04c MUX_M0 /* CSI1_PWD_N */
67 0x080 MUX_M0 /* GPIO_034 */
93 0x11c MUX_M0 /* GPIO_073 */
94 0x120 MUX_M0 /* GPIO_074 */
161 0x0c8 MUX_M0 /* CAM0_RST */
167 0x124 MUX_M0 /* CAM1_RST */
A Dhikey970-pinctrl.dtsi81 0x714 MUX_M0 /* CAM0_RST */
87 0x048 MUX_M0 /* CAM1_RST */
93 0x098 MUX_M0 /* CAM0_PWD_N */
99 0x044 MUX_M0 /* CAM1_PWD_N */
132 0x064 MUX_M0 /* GPIO_203 */
138 0x080 MUX_M0 /* GPIO_221 */
A Dhi6220.dtsi414 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
415 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
416 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
417 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
418 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
419 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
/linux/include/dt-bindings/pinctrl/
A Dhisi.h21 #define MUX_M0 0 macro

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