Home
last modified time | relevance | path

Searched refs:NAND (Results 1 – 25 of 246) sorted by relevance

12345678910

/linux/drivers/mtd/nand/raw/
A DKconfig24 Denali NAND controller core.
31 Enable the driver for NAND flash on platforms using a Denali NAND
134 tristate "Atmel AT91 NAND Flash/SmartMedia NAND controller"
174 by the SLC NAND controller.
186 by the MLC NAND controller.
251 external NAND devices.
263 external NAND devices.
299 for NAND Flash using FLCTL.
336 Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
358 Enables support for NAND flash chips on SoCs containing the EBI2 NAND
[all …]
/linux/Documentation/devicetree/bindings/mtd/
A Dbrcm,brcmnand.yaml7 title: Broadcom STB NAND Controller
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
25 -- Additional SoC-specific NAND controller properties --
37 register resources within the NAND controller node above.
56 - description: BCM63138 SoC-specific NAND controller
63 - description: iProc SoC-specific NAND controller
68 - description: BCM63168 SoC-specific NAND controller
88 - description: NAND CTLRDY interrupt
101 description: reference to the clock for the NAND controller
132 the flash geometry (particularly the NAND page
[all …]
A Dmtk-nand.txt1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
24 - #address-cells: NAND chip index, should be 1.
42 - children nodes: NAND chips.
48 - nand-on-flash-bbt: Store BBT on NAND Flash.
74 According to MTK NAND controller design,
76 that MTK NAND controller supports.
85 - pinctrl-names: Default NAND pin GPIO setting name.
[all …]
A Datmel-nand.txt1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
30 * NAND device/chip bindings:
33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
36 1st entry: the CS line this NAND chip is connected to
42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
50 device node, and NAND partitions should be defined under the NAND node as
[all …]
A Dnand-controller.yaml7 title: NAND Chip and NAND Controller Generic Binding
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
47 NAND controller (even if they are not used). As many additional
49 lines. 'reg' entries of the NAND chip subnodes become indexes of
66 1/ The ECC engine is part of the NAND controller, in this
68 2/ The ECC engine is part of the NAND part (on-die), in this
99 Bus width to the NAND chip
136 want to make your NAND as reliable as possible.
[all …]
A Doxnas-nand.txt1 * Oxford Semiconductor OXNAS NAND Controller
3 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
7 - reg: Base address and length for NAND mapped memory.
10 - clocks: phandle to the NAND gate clock if needed.
11 - resets: phandle to the NAND reset control if needed.
A Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
41 Optional child node of NAND chip nodes:
A Dfsmc-nand.txt2 NAND Interface
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
47 0xd2000000 0x0010 /* NAND Base DATA */
48 0xd2020000 0x0010 /* NAND Base ADDR */
49 0xd2010000 0x0010>; /* NAND Base CMD */
A Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
16 - interrupts: shall define the NAND controller interrupt.
17 - clocks: shall reference the NAND controller clocks, the second one is
22 NAND controller related registers (only required with the
27 - dmas: shall reference DMA channel associated to the NAND controller.
35 Children nodes represent the available NAND chips.
52 the NAND chip. This value may be overwritten with nand-ecc-strength
55 - nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
A Dgpio-control-nand.txt1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
10 resource describes the data bus connected to the NAND flash and all accesses
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
24 the GPIO's and the NAND flash data bus. If present, then after changing
A Dvf610-nfc.txt1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
24 only handle one NAND chip.
A Ddavinci-nand.txt1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller
4 NAND interface contains.
29 address for the chip select space the NAND Flash
35 address for the chip select space the NAND Flash
42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
58 - ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
71 the address space. See partition.txt for more detail. The NAND Flash timing
A Dti,gpmc-nand.yaml7 title: Texas Instruments GPMC NAND Flash controller.
14 GPMC NAND controller/Flash is represented as a child of the
51 Bus width to the NAND chip
105 /* NAND generic properties */
113 label = "NAND.SPL";
117 label = "NAND.SPL.backup1";
A Dlpc32xx-mlc.txt1 NXP LPC32xx SoC NAND MLC controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
A Dingenic,nand.yaml7 title: Ingenic SoCs NAND controller devicetree bindings
24 - description: Bank number, offset and size of first attached NAND chip
25 - description: Bank number, offset and size of second attached NAND chip
26 - description: Bank number, offset and size of third attached NAND chip
27 - description: Bank number, offset and size of fourth attached NAND chip
/linux/drivers/pinctrl/tegra/
A Dpinctrl-tegra30.c2197 …PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, …
2222 …PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, …
2223 …PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, …
2224 …PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, …
2225 …PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, …
2226 …PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, …
2227 …PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, …
2228 …PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, …
2229 …PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, …
2230 …PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, …
[all …]
A Dpinctrl-tegra114.c1665 …PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N…
1667 …PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, 0x31c8, N, N…
1668 …PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, 0x31cc, N, N…
1669 …PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, 0x31d0, N, N…
1670 …PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, 0x31d4, N, N…
1671 …PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, 0x31d8, N, N…
1672 …PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, 0x31dc, N, N…
1673 …PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, 0x31e0, N, N…
1674 …PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, 0x31e4, N, N…
1675 …PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, 0x31e8, N, N…
[all …]
/linux/Documentation/arm/samsung-s3c24xx/
A Dnand.rst2 S3C24XX NAND Support
8 Small Page NAND
15 Large Page NAND
18 The driver is capable of handling NAND flash with a 2KiB page
/linux/arch/powerpc/boot/dts/fsl/
A Dp1010rdb-pa.dtsi40 label = "NAND U-Boot Image";
47 label = "NAND DTB Image";
53 label = "NAND Linux Kernel Image";
59 label = "NAND Compressed RFS Image";
65 label = "NAND JFFS2 Root File System";
71 label = "NAND User area";
/linux/drivers/mtd/nand/
A DKconfig3 menu "NAND" menu
26 widely used with old parts, newer NAND chips usually require
31 bool "NAND ECC Smart Media byte order"
46 ECC codes. They are used with NAND devices requiring more than 1 bit
/linux/arch/arm64/boot/dts/marvell/
A Dcn9130-db.dts14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
A Dcn9131-db.dts14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
A Dcn9132-db-B.dts14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
A Dcn9132-db.dts14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
A Dcn9130-db-B.dts14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.

Completed in 37 milliseconds

12345678910