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Searched refs:ODT (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
85 ODT = ram->next->bios.timing_10_ODT; in nvkm_sddr3_calc()
92 ODT = (ram->mr[1] & 0x004) >> 2 | in nvkm_sddr3_calc()
112 ram->mr[1] |= (ODT & 0x1) << 2; in nvkm_sddr3_calc()
113 ram->mr[1] |= (ODT & 0x2) << 5; in nvkm_sddr3_calc()
114 ram->mr[1] |= (ODT & 0x4) << 7; in nvkm_sddr3_calc()
A Dsddr2.c63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
70 ODT = ram->next->bios.timing_10_ODT & 3; in nvkm_sddr2_calc()
82 ODT = (ram->mr[1] & 0x004) >> 2 | in nvkm_sddr2_calc()
96 ram->mr[1] |= (ODT & 0x1) << 2; in nvkm_sddr2_calc()
97 ram->mr[1] |= (ODT & 0x2) << 5; in nvkm_sddr2_calc()
A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
81 ODT = ram->next->bios.timing_10_ODT; in nvkm_gddr3_calc()
98 ODT = (ram->mr[1] & 0xc) >> 2; in nvkm_gddr3_calc()
113 ram->mr[1] |= (ODT & 0x03) << 2; in nvkm_gddr3_calc()
/linux/Documentation/devicetree/bindings/devfreq/
A Drk3399_dmc.txt72 Note: PHY DLL and PHY ODT are independent.
75 the ODT disable frequency in MHz (Mega Hz).
77 the ODT on the DRAM side and controller side are
85 the DRAM side ODT strength in ohms. Default value
98 the PHY side ODT strength. Default value is 240.
101 then ODT disable frequency in MHz (Mega Hz).
103 the ODT on the DRAM side and controller side are
127 defines the ODT disable frequency in
129 ddr3_odt_dis_freq, the ODT on the DRAM side and
141 the DRAM side ODT on CA line strength in ohms.
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