1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_MACH_REGS_OST_H 3 #define __ASM_MACH_REGS_OST_H 4 5 #include <mach/hardware.h> 6 7 /* 8 * OS Timer & Match Registers 9 */ 10 11 #define OSMR0 io_p2v(0x40A00000) /* */ 12 #define OSMR1 io_p2v(0x40A00004) /* */ 13 #define OSMR2 io_p2v(0x40A00008) /* */ 14 #define OSMR3 io_p2v(0x40A0000C) /* */ 15 #define OSMR4 io_p2v(0x40A00080) /* */ 16 #define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */ 17 #define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */ 18 #define OMCR4 io_p2v(0x40A000C0) /* */ 19 #define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */ 20 #define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */ 21 #define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */ 22 23 #define OSSR_M3 (1 << 3) /* Match status channel 3 */ 24 #define OSSR_M2 (1 << 2) /* Match status channel 2 */ 25 #define OSSR_M1 (1 << 1) /* Match status channel 1 */ 26 #define OSSR_M0 (1 << 0) /* Match status channel 0 */ 27 28 #define OWER_WME (1 << 0) /* Watchdog Match Enable */ 29 30 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ 31 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ 32 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ 33 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ 34 35 #endif /* __ASM_MACH_REGS_OST_H */ 36