Home
last modified time | relevance | path

Searched refs:OUT_RING (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/r128/
A Dr128_state.c57 OUT_RING(boxes[0].x1); in r128_emit_clip_rects()
59 OUT_RING(boxes[0].y1); in r128_emit_clip_rects()
66 OUT_RING(boxes[1].x1); in r128_emit_clip_rects()
68 OUT_RING(boxes[1].y1); in r128_emit_clip_rects()
84 OUT_RING(aux_sc_cntl); in r128_emit_clip_rects()
320 OUT_RING(color); in r128_clear_box()
605 OUT_RING(offset); in r128_cce_dispatch_vertex()
606 OUT_RING(size); in r128_cce_dispatch_vertex()
607 OUT_RING(format); in r128_cce_dispatch_vertex()
669 OUT_RING(offset); in r128_cce_dispatch_indirect()
[all …]
A Dr128_drv.h477 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \
478 OUT_RING(R128_EVENT_CRTC_OFFSET); \
536 #define OUT_RING(x) do { \ macro
/linux/drivers/gpu/drm/i810/
A Di810_dma.c486 OUT_RING(0); in i810EmitContextVerified()
554 OUT_RING(0); in i810EmitDestVerified()
805 OUT_RING(0); in i810_dma_dispatch_flip()
821 OUT_RING(0); in i810_dma_dispatch_flip()
826 OUT_RING(0); in i810_dma_dispatch_flip()
847 OUT_RING(0); in i810_dma_quiescent()
848 OUT_RING(0); in i810_dma_quiescent()
865 OUT_RING(0); in i810_flush_queue()
1074 OUT_RING(0); in i810_dma_dispatch_mc()
1081 OUT_RING(0); in i810_dma_dispatch_mc()
[all …]
A Di810_drv.h166 #define OUT_RING(n) do { \ macro
/linux/drivers/gpu/drm/msm/adreno/
A Da2xx_gpu.c43 OUT_RING(ring, 0x00000000); in a2xx_submit()
50 OUT_RING(ring, 0x80000000); in a2xx_submit()
62 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
64 OUT_RING(ring, 0x00000000); in a2xx_me_init()
66 OUT_RING(ring, 0x00000000); in a2xx_me_init()
79 OUT_RING(ring, 0x80000180); in a2xx_me_init()
81 OUT_RING(ring, 0x00000001); in a2xx_me_init()
84 OUT_RING(ring, 0x00000000); in a2xx_me_init()
86 OUT_RING(ring, 0x00000000); in a2xx_me_init()
88 OUT_RING(ring, 0x200001f2); in a2xx_me_init()
[all …]
A Da3xx_gpu.c64 OUT_RING(ring, HLSQ_FLUSH); in a3xx_submit()
68 OUT_RING(ring, 0x00000000); in a3xx_submit()
80 OUT_RING(ring, 0x00000000); in a3xx_submit()
91 OUT_RING(ring, 0x000003f7); in a3xx_me_init()
92 OUT_RING(ring, 0x00000000); in a3xx_me_init()
93 OUT_RING(ring, 0x00000000); in a3xx_me_init()
94 OUT_RING(ring, 0x00000000); in a3xx_me_init()
95 OUT_RING(ring, 0x00000080); in a3xx_me_init()
96 OUT_RING(ring, 0x00000100); in a3xx_me_init()
97 OUT_RING(ring, 0x00000180); in a3xx_me_init()
[all …]
A Da4xx_gpu.c58 OUT_RING(ring, HLSQ_FLUSH); in a4xx_submit()
62 OUT_RING(ring, 0x00000000); in a4xx_submit()
162 OUT_RING(ring, 0x000003f7); in a4xx_me_init()
163 OUT_RING(ring, 0x00000000); in a4xx_me_init()
164 OUT_RING(ring, 0x00000000); in a4xx_me_init()
165 OUT_RING(ring, 0x00000000); in a4xx_me_init()
166 OUT_RING(ring, 0x00000080); in a4xx_me_init()
167 OUT_RING(ring, 0x00000100); in a4xx_me_init()
168 OUT_RING(ring, 0x00000180); in a4xx_me_init()
169 OUT_RING(ring, 0x00006600); in a4xx_me_init()
[all …]
A Da5xx_gpu.c140 OUT_RING(ring, 0x02); in a5xx_submit()
144 OUT_RING(ring, 0); in a5xx_submit()
153 OUT_RING(ring, 1); in a5xx_submit()
157 OUT_RING(ring, 0x02); in a5xx_submit()
198 OUT_RING(ring, 0); in a5xx_submit()
199 OUT_RING(ring, 0); in a5xx_submit()
200 OUT_RING(ring, 0); in a5xx_submit()
201 OUT_RING(ring, 0); in a5xx_submit()
202 OUT_RING(ring, 0); in a5xx_submit()
520 OUT_RING(ring, 0); in a5xx_preempt_start()
[all …]
A Da6xx_gpu.c119 OUT_RING(ring, in a6xx_set_pagetable()
140 OUT_RING(ring, 0x31); in a6xx_set_pagetable()
210 OUT_RING(ring, submit->seqno); in a6xx_submit()
733 OUT_RING(ring, 0x0000002f); in a6xx_cp_init()
736 OUT_RING(ring, 0x00000003); in a6xx_cp_init()
739 OUT_RING(ring, 0x20000000); in a6xx_cp_init()
742 OUT_RING(ring, 0x00000000); in a6xx_cp_init()
743 OUT_RING(ring, 0x00000000); in a6xx_cp_init()
746 OUT_RING(ring, 0x00000000); in a6xx_cp_init()
749 OUT_RING(ring, 0x00000000); in a6xx_cp_init()
[all …]
A Da5xx_power.c231 OUT_RING(ring, 0); in a5xx_gpmu_init()
235 OUT_RING(ring, lower_32_bits(a5xx_gpu->gpmu_iova)); in a5xx_gpmu_init()
236 OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova)); in a5xx_gpmu_init()
237 OUT_RING(ring, a5xx_gpu->gpmu_dwords); in a5xx_gpmu_init()
241 OUT_RING(ring, 1); in a5xx_gpmu_init()
A Dadreno_gpu.h332 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); in OUT_PKT0()
340 OUT_RING(ring, CP_TYPE2_PKT); in OUT_PKT2()
347 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); in OUT_PKT3()
369 OUT_RING(ring, PKT4(regindx, cnt)); in OUT_PKT4()
376 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | in OUT_PKT7()
/linux/drivers/video/fbdev/intelfb/
A Dintelfbhw.c1687 OUT_RING(br00); in intelfbhw_do_fillrect()
1688 OUT_RING(br13); in intelfbhw_do_fillrect()
1689 OUT_RING(br14); in intelfbhw_do_fillrect()
1690 OUT_RING(br09); in intelfbhw_do_fillrect()
1691 OUT_RING(br16); in intelfbhw_do_fillrect()
1736 OUT_RING(br00); in intelfbhw_do_bitblt()
1737 OUT_RING(br13); in intelfbhw_do_bitblt()
1738 OUT_RING(br22); in intelfbhw_do_bitblt()
1739 OUT_RING(br23); in intelfbhw_do_bitblt()
1740 OUT_RING(br09); in intelfbhw_do_bitblt()
[all …]
A Dintelfbhw.h534 #define OUT_RING(n) do { \ macro
/linux/drivers/gpu/drm/msm/
A Dmsm_ringbuffer.h82 OUT_RING(struct msm_ringbuffer *ring, uint32_t data) in OUT_RING() function
/linux/drivers/gpu/drm/nouveau/
A Dnouveau_dma.h72 OUT_RING(struct nouveau_channel *chan, int data) in OUT_RING() function
A Dnouveau_dma.c212 OUT_RING(chan, chan->push.addr | 0x20000000); in nouveau_dma_wait()

Completed in 37 milliseconds