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Searched refs:PACKET3_SET_CONTEXT_REG (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dsi_enums.h262 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Dsoc15d.h288 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Dnvd.h321 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Dvid.h342 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Dcikd.h460 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Dgfx_v7_0.c2560 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v7_0_cp_gfx_start()
2568 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_cp_gfx_start()
2579 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_cp_gfx_start()
4008 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v7_0_get_csb_buffer()
4018 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_get_csb_buffer()
A Dgfx_v6_0.c2062 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v6_0_cp_gfx_start()
2076 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v6_0_cp_gfx_start()
2896 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v6_0_get_csb_buffer()
2906 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in gfx_v6_0_get_csb_buffer()
A Dsid.h1848 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Dgfx_v8_0.c1275 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v8_0_get_csb_buffer()
1286 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_get_csb_buffer()
4213 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v8_0_cp_gfx_start()
4223 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_cp_gfx_start()
A Dgfx_v10_0.c4414 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v10_0_get_csb_buffer()
4427 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in gfx_v10_0_get_csb_buffer()
6242 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v10_0_cp_gfx_start()
6254 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in gfx_v10_0_cp_gfx_start()
A Dgfx_v9_0.c1778 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v9_0_get_csb_buffer()
3295 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v9_0_cp_gfx_start()
/linux/drivers/gpu/drm/radeon/
A Dnid.h1272 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Dsi.c3604 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in si_cp_start()
4571 case PACKET3_SET_CONTEXT_REG: in si_vm_packet3_gfx_check()
4674 case PACKET3_SET_CONTEXT_REG: in si_vm_packet3_compute_check()
5732 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in si_get_csb_buffer()
5742 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in si_get_csb_buffer()
A Dsid.h1785 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Dcikd.h1928 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Devergreen_cs.c2316 case PACKET3_SET_CONTEXT_REG: in evergreen_packet3_check()
3395 case PACKET3_SET_CONTEXT_REG: in evergreen_vm_packet3_check()
A Devergreend.h1668 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Dr600d.h1689 #define PACKET3_SET_CONTEXT_REG 0x69 macro
A Dr600_cs.c1926 case PACKET3_SET_CONTEXT_REG: in r600_packet3_check()
A Dcik.c4013 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_cp_gfx_start()
6721 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in cik_get_csb_buffer()
6731 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_get_csb_buffer()

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