1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_SH_HITACHI_SE_H
3 #define __ASM_SH_HITACHI_SE_H
4 
5 /*
6  * linux/include/asm-sh/hitachi_se.h
7  *
8  * Copyright (C) 2000  Kazumoto Kojima
9  *
10  * Hitachi SolutionEngine support
11  */
12 #include <linux/sh_intc.h>
13 
14 /* Box specific addresses.  */
15 
16 #define PA_ROM		0x00000000	/* EPROM */
17 #define PA_ROM_SIZE	0x00400000	/* EPROM size 4M byte */
18 #define PA_FROM		0x01000000	/* EPROM */
19 #define PA_FROM_SIZE	0x00400000	/* EPROM size 4M byte */
20 #define PA_EXT1		0x04000000
21 #define PA_EXT1_SIZE	0x04000000
22 #define PA_EXT2		0x08000000
23 #define PA_EXT2_SIZE	0x04000000
24 #define PA_SDRAM	0x0c000000
25 #define PA_SDRAM_SIZE	0x04000000
26 
27 #define PA_EXT4		0x12000000
28 #define PA_EXT4_SIZE	0x02000000
29 #define PA_EXT5		0x14000000
30 #define PA_EXT5_SIZE	0x04000000
31 #define PA_PCIC		0x18000000	/* MR-SHPC-01 PCMCIA */
32 
33 #define PA_83902	0xb0000000	/* DP83902A */
34 #define PA_83902_IF	0xb0040000	/* DP83902A remote io port */
35 #define PA_83902_RST	0xb0080000	/* DP83902A reset port */
36 
37 #define PA_SUPERIO	0xb0400000	/* SMC37C935A super io chip */
38 #define PA_DIPSW0	0xb0800000	/* Dip switch 5,6 */
39 #define PA_DIPSW1	0xb0800002	/* Dip switch 7,8 */
40 #define PA_LED		0xb0c00000	/* LED */
41 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
42 #define PA_BCR		0xb0e00000
43 #else
44 #define PA_BCR		0xb1400000	/* FPGA */
45 #endif
46 
47 #define PA_MRSHPC	0xb83fffe0	/* MR-SHPC-01 PCMCIA controller */
48 #define PA_MRSHPC_MW1	0xb8400000	/* MR-SHPC-01 memory window base */
49 #define PA_MRSHPC_MW2	0xb8500000	/* MR-SHPC-01 attribute window base */
50 #define PA_MRSHPC_IO	0xb8600000	/* MR-SHPC-01 I/O window base */
51 #define MRSHPC_OPTION   (PA_MRSHPC + 6)
52 #define MRSHPC_CSR      (PA_MRSHPC + 8)
53 #define MRSHPC_ISR      (PA_MRSHPC + 10)
54 #define MRSHPC_ICR      (PA_MRSHPC + 12)
55 #define MRSHPC_CPWCR    (PA_MRSHPC + 14)
56 #define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
57 #define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
58 #define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
59 #define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
60 #define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
61 #define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
62 #define MRSHPC_CDCR     (PA_MRSHPC + 28)
63 #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
64 
65 #define BCR_ILCRA	(PA_BCR + 0)
66 #define BCR_ILCRB	(PA_BCR + 2)
67 #define BCR_ILCRC	(PA_BCR + 4)
68 #define BCR_ILCRD	(PA_BCR + 6)
69 #define BCR_ILCRE	(PA_BCR + 8)
70 #define BCR_ILCRF	(PA_BCR + 10)
71 #define BCR_ILCRG	(PA_BCR + 12)
72 
73 #if defined(CONFIG_CPU_SUBTYPE_SH7709)
74 #define INTC_IRR0       0xa4000004UL
75 #define INTC_IRR1       0xa4000006UL
76 #define INTC_IRR2       0xa4000008UL
77 
78 #define INTC_ICR0       0xfffffee0UL
79 #define INTC_ICR1       0xa4000010UL
80 #define INTC_ICR2       0xa4000012UL
81 #define INTC_INTER      0xa4000014UL
82 
83 #define INTC_IPRC       0xa4000016UL
84 #define INTC_IPRD       0xa4000018UL
85 #define INTC_IPRE       0xa400001aUL
86 
87 #define IRQ0_IRQ        evt2irq(0x600)
88 #define IRQ1_IRQ        evt2irq(0x620)
89 #endif
90 
91 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
92 #define IRQ_STNIC	evt2irq(0x380)
93 #define IRQ_CFCARD	evt2irq(0x3c0)
94 #else
95 #define IRQ_STNIC	evt2irq(0x340)
96 #define IRQ_CFCARD	evt2irq(0x2e0)
97 #endif
98 
99 /* SH Ether support (SH7710/SH7712) */
100 /* Base address */
101 #define SH_ETH0_BASE 0xA7000000
102 #define SH_ETH1_BASE 0xA7000400
103 #define SH_TSU_BASE  0xA7000800
104 /* PHY ID */
105 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
106 # define PHY_ID 0x00
107 #elif defined(CONFIG_CPU_SUBTYPE_SH7712)
108 # define PHY_ID 0x01
109 #endif
110 /* Ether IRQ */
111 #define SH_ETH0_IRQ	evt2irq(0xc00)
112 #define SH_ETH1_IRQ	evt2irq(0xc20)
113 #define SH_TSU_IRQ	evt2irq(0xc40)
114 
115 void init_se_IRQ(void);
116 
117 #define __IO_PREFIX	se
118 #include <asm/io_generic.h>
119 
120 #endif  /* __ASM_SH_HITACHI_SE_H */
121