1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h 4 * 5 * Register definitions for IXP4xx chipset. This file contains 6 * register location and bit definitions only. Platform specific 7 * definitions and helper function declarations are in platform.h 8 * and machine-name.h. 9 * 10 * Copyright (C) 2002 Intel Corporation. 11 * Copyright (C) 2003-2004 MontaVista Software, Inc. 12 */ 13 14 #ifndef _ASM_ARM_IXP4XX_H_ 15 #define _ASM_ARM_IXP4XX_H_ 16 17 /* 18 * IXP4xx Linux Memory Map: 19 * 20 * Phy Size Virt Description 21 * ========================================================================= 22 * 23 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM 24 * 25 * 0x48000000 0x04000000 ioremap'd PCI Memory Space 26 * 27 * 0x50000000 0x10000000 ioremap'd EXP BUS 28 * 29 * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals 30 * 31 * 0xC0000000 0x00001000 0xFEF13000 PCI CFG 32 * 33 * 0xC4000000 0x00001000 0xFEF14000 EXP CFG 34 * 35 * 0x60000000 0x00004000 0xFEF15000 QMgr 36 */ 37 38 /* 39 * Queue Manager 40 */ 41 #define IXP4XX_QMGR_BASE_PHYS 0x60000000 42 43 /* 44 * Peripheral space, including debug UART. Must be section-aligned so that 45 * it can be used with the low-level debug code. 46 */ 47 #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 48 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000) 49 #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 50 51 /* 52 * PCI Config registers 53 */ 54 #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 55 #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000) 56 #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 57 58 /* 59 * Expansion BUS Configuration registers 60 */ 61 #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 62 #define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000 63 #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 64 65 #define IXP4XX_EXP_CS0_OFFSET 0x00 66 #define IXP4XX_EXP_CS1_OFFSET 0x04 67 #define IXP4XX_EXP_CS2_OFFSET 0x08 68 #define IXP4XX_EXP_CS3_OFFSET 0x0C 69 #define IXP4XX_EXP_CS4_OFFSET 0x10 70 #define IXP4XX_EXP_CS5_OFFSET 0x14 71 #define IXP4XX_EXP_CS6_OFFSET 0x18 72 #define IXP4XX_EXP_CS7_OFFSET 0x1C 73 #define IXP4XX_EXP_CFG0_OFFSET 0x20 74 #define IXP4XX_EXP_CFG1_OFFSET 0x24 75 #define IXP4XX_EXP_CFG2_OFFSET 0x28 76 #define IXP4XX_EXP_CFG3_OFFSET 0x2C 77 78 /* 79 * Expansion Bus Controller registers. 80 */ 81 #define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) 82 83 #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) 84 #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) 85 #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) 86 #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET) 87 #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET) 88 #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET) 89 #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET) 90 #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET) 91 92 #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) 93 #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) 94 #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) 95 #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET) 96 97 98 /* 99 * Peripheral Space Register Region Base Addresses 100 */ 101 #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) 102 #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) 103 #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) 104 #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) 105 #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) 106 #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) 107 #define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000) 108 #define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000) 109 #define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000) 110 #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) 111 #define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) 112 #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) 113 /* ixp46X only */ 114 #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000) 115 #define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000) 116 #define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000) 117 #define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000) 118 #define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000) 119 #define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000) 120 #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) 121 122 123 /* The UART is explicitly put in the beginning of fixmap */ 124 #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) 125 #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) 126 #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) 127 #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) 128 #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) 129 #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) 130 #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) 131 #define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) 132 #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) 133 /* ixp46X only */ 134 #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000) 135 #define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000) 136 #define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000) 137 #define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000) 138 #define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000) 139 #define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000) 140 #define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000) 141 142 /* 143 * Constants to make it easy to access Timer Control/Status registers 144 */ 145 #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */ 146 #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ 147 #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ 148 #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ 149 #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ 150 #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */ 151 #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */ 152 #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */ 153 #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */ 154 155 /* 156 * Operating System Timer Register Definitions. 157 */ 158 159 #define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x))) 160 161 #define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET) 162 #define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET) 163 #define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET) 164 #define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET) 165 #define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET) 166 #define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET) 167 #define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET) 168 #define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET) 169 #define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET) 170 171 /* 172 * Timer register values and bit definitions 173 */ 174 #define IXP4XX_OST_ENABLE 0x00000001 175 #define IXP4XX_OST_ONE_SHOT 0x00000002 176 /* Low order bits of reload value ignored */ 177 #define IXP4XX_OST_RELOAD_MASK 0x00000003 178 #define IXP4XX_OST_DISABLED 0x00000000 179 #define IXP4XX_OSST_TIMER_1_PEND 0x00000001 180 #define IXP4XX_OSST_TIMER_2_PEND 0x00000002 181 #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004 182 #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008 183 #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010 184 185 #define IXP4XX_WDT_KEY 0x0000482E 186 187 #define IXP4XX_WDT_RESET_ENABLE 0x00000001 188 #define IXP4XX_WDT_IRQ_ENABLE 0x00000002 189 #define IXP4XX_WDT_COUNT_ENABLE 0x00000004 190 191 192 /* 193 * Constants to make it easy to access PCI Control/Status registers 194 */ 195 #define PCI_NP_AD_OFFSET 0x00 196 #define PCI_NP_CBE_OFFSET 0x04 197 #define PCI_NP_WDATA_OFFSET 0x08 198 #define PCI_NP_RDATA_OFFSET 0x0c 199 #define PCI_CRP_AD_CBE_OFFSET 0x10 200 #define PCI_CRP_WDATA_OFFSET 0x14 201 #define PCI_CRP_RDATA_OFFSET 0x18 202 #define PCI_CSR_OFFSET 0x1c 203 #define PCI_ISR_OFFSET 0x20 204 #define PCI_INTEN_OFFSET 0x24 205 #define PCI_DMACTRL_OFFSET 0x28 206 #define PCI_AHBMEMBASE_OFFSET 0x2c 207 #define PCI_AHBIOBASE_OFFSET 0x30 208 #define PCI_PCIMEMBASE_OFFSET 0x34 209 #define PCI_AHBDOORBELL_OFFSET 0x38 210 #define PCI_PCIDOORBELL_OFFSET 0x3C 211 #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 212 #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 213 #define PCI_ATPDMA0_LENADDR_OFFSET 0x48 214 #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C 215 #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 216 #define PCI_ATPDMA1_LENADDR_OFFSET 0x54 217 218 /* 219 * PCI Control/Status Registers 220 */ 221 #define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) 222 223 #define PCI_NP_AD _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) 224 #define PCI_NP_CBE _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) 225 #define PCI_NP_WDATA _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) 226 #define PCI_NP_RDATA _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) 227 #define PCI_CRP_AD_CBE _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) 228 #define PCI_CRP_WDATA _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) 229 #define PCI_CRP_RDATA _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) 230 #define PCI_CSR _IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 231 #define PCI_ISR _IXP4XX_PCI_CSR(PCI_ISR_OFFSET) 232 #define PCI_INTEN _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) 233 #define PCI_DMACTRL _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) 234 #define PCI_AHBMEMBASE _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) 235 #define PCI_AHBIOBASE _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) 236 #define PCI_PCIMEMBASE _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) 237 #define PCI_AHBDOORBELL _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) 238 #define PCI_PCIDOORBELL _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) 239 #define PCI_ATPDMA0_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) 240 #define PCI_ATPDMA0_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) 241 #define PCI_ATPDMA0_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) 242 #define PCI_ATPDMA1_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) 243 #define PCI_ATPDMA1_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) 244 #define PCI_ATPDMA1_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) 245 246 /* 247 * PCI register values and bit definitions 248 */ 249 250 /* CSR bit definitions */ 251 #define PCI_CSR_HOST 0x00000001 252 #define PCI_CSR_ARBEN 0x00000002 253 #define PCI_CSR_ADS 0x00000004 254 #define PCI_CSR_PDS 0x00000008 255 #define PCI_CSR_ABE 0x00000010 256 #define PCI_CSR_DBT 0x00000020 257 #define PCI_CSR_ASE 0x00000100 258 #define PCI_CSR_IC 0x00008000 259 260 /* ISR (Interrupt status) Register bit definitions */ 261 #define PCI_ISR_PSE 0x00000001 262 #define PCI_ISR_PFE 0x00000002 263 #define PCI_ISR_PPE 0x00000004 264 #define PCI_ISR_AHBE 0x00000008 265 #define PCI_ISR_APDC 0x00000010 266 #define PCI_ISR_PADC 0x00000020 267 #define PCI_ISR_ADB 0x00000040 268 #define PCI_ISR_PDB 0x00000080 269 270 /* INTEN (Interrupt Enable) Register bit definitions */ 271 #define PCI_INTEN_PSE 0x00000001 272 #define PCI_INTEN_PFE 0x00000002 273 #define PCI_INTEN_PPE 0x00000004 274 #define PCI_INTEN_AHBE 0x00000008 275 #define PCI_INTEN_APDC 0x00000010 276 #define PCI_INTEN_PADC 0x00000020 277 #define PCI_INTEN_ADB 0x00000040 278 #define PCI_INTEN_PDB 0x00000080 279 280 /* 281 * Shift value for byte enable on NP cmd/byte enable register 282 */ 283 #define IXP4XX_PCI_NP_CBE_BESL 4 284 285 /* 286 * PCI commands supported by NP access unit 287 */ 288 #define NP_CMD_IOREAD 0x2 289 #define NP_CMD_IOWRITE 0x3 290 #define NP_CMD_CONFIGREAD 0xa 291 #define NP_CMD_CONFIGWRITE 0xb 292 #define NP_CMD_MEMREAD 0x6 293 #define NP_CMD_MEMWRITE 0x7 294 295 /* 296 * Constants for CRP access into local config space 297 */ 298 #define CRP_AD_CBE_BESL 20 299 #define CRP_AD_CBE_WRITE 0x00010000 300 301 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ 302 303 #endif 304