Searched refs:PHYASYMCLK_CLOCK_CNTL (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dccg.h | 34 SR(PHYASYMCLK_CLOCK_CNTL),\
45 SR(PHYASYMCLK_CLOCK_CNTL),\
53 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
54 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
62 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
63 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_dccg.h | 41 SR(PHYASYMCLK_CLOCK_CNTL),\
84 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
85 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
|
| A D | dcn31_dccg.c | 410 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
414 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dccg.h | 215 uint32_t PHYASYMCLK_CLOCK_CNTL; member
|
Completed in 7 milliseconds