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Searched refs:PHYESYMCLK_CLOCK_CNTL (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_dccg.h45 SR(PHYESYMCLK_CLOCK_CNTL),\
92 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
93 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
A Ddcn31_dccg.c450 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
454 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dccg.h219 uint32_t PHYESYMCLK_CLOCK_CNTL; member

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