/linux/drivers/gpu/drm/i915/gvt/ |
A D | handlers.c | 2285 MMIO_D(PIPEDSL(PIPE_A), D_ALL); in init_generic_mmio_info() 2310 MMIO_D(CURCNTR(PIPE_A), D_ALL); in init_generic_mmio_info() 2314 MMIO_D(CURPOS(PIPE_A), D_ALL); in init_generic_mmio_info() 2318 MMIO_D(CURBASE(PIPE_A), D_ALL); in init_generic_mmio_info() 2335 MMIO_D(DSPCNTR(PIPE_A), D_ALL); in init_generic_mmio_info() 2336 MMIO_D(DSPADDR(PIPE_A), D_ALL); in init_generic_mmio_info() 2338 MMIO_D(DSPPOS(PIPE_A), D_ALL); in init_generic_mmio_info() 2339 MMIO_D(DSPSIZE(PIPE_A), D_ALL); in init_generic_mmio_info() 2368 MMIO_D(SPRCTL(PIPE_A), D_ALL); in init_generic_mmio_info() 2371 MMIO_D(SPRPOS(PIPE_A), D_ALL); in init_generic_mmio_info() [all …]
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A D | display.c | 46 pipe = PIPE_A; in get_edp_pipe() 75 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled() 247 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change() 248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE; in emulate_monitor_status_change() 505 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change() 623 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe() 629 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
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A D | reg.h | 72 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \ 82 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
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/linux/drivers/gpu/drm/i915/ |
A D | i915_pci.c | 97 [PIPE_A] = CURSOR_A_OFFSET, \ 102 [PIPE_A] = CURSOR_A_OFFSET, \ 108 [PIPE_A] = CURSOR_A_OFFSET, \ 115 [PIPE_A] = CURSOR_A_OFFSET, \ 122 [PIPE_A] = CURSOR_A_OFFSET, \ 160 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 181 .pipe_mask = BIT(PIPE_A), \ 223 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 313 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 511 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), [all …]
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A D | intel_pm.c | 511 case PIPE_A: in vlv_get_fifo_size() 2044 case PIPE_A: in vlv_atomic_update_fifo() 4428 [PIPE_A] = BIT(DBUF_S1), 4440 [PIPE_A] = BIT(DBUF_S1), 4453 [PIPE_A] = BIT(DBUF_S1), 4467 [PIPE_A] = BIT(DBUF_S1), 4503 [PIPE_A] = BIT(DBUF_S2), 4516 [PIPE_A] = BIT(DBUF_S1), 4530 [PIPE_A] = BIT(DBUF_S1), 4544 [PIPE_A] = BIT(DBUF_S1), [all …]
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A D | intel_device_info.c | 272 runtime->num_scalers[PIPE_A] = 2; in intel_device_info_runtime_init() 298 runtime->num_sprites[PIPE_A] = 2; in intel_device_info_runtime_init() 340 info->pipe_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
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A D | i915_trace.h | 45 __entry->frame[PIPE_A], __entry->scanline[PIPE_A], 72 __entry->frame[PIPE_A], __entry->scanline[PIPE_A], 169 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
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A D | i915_irq.c | 613 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat() 1458 case PIPE_A: in i9xx_pipestat_irq_ack() 1893 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler() 2411 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler() 3040 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall() 3957 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall() 4136 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall() 4256 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall() 4257 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
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/linux/drivers/gpu/drm/i915/display/ |
A D | intel_fdi.c | 155 case PIPE_A: in ilk_check_fdi_lanes() 306 case PIPE_A: in ivb_update_fdi_bc_bifurcation() 781 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train() 789 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train() 826 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train() 832 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train() 834 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train() 835 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train() 858 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train() 875 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train() [all …]
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A D | g4x_hdmi.c | 323 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi() 324 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi() 327 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi() 341 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_hdmi() 342 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi() 343 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi() 596 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
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A D | intel_cursor.c | 285 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); in i845_update_cursor() 286 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); in i845_update_cursor() 288 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_update_cursor() 289 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); in i845_update_cursor() 295 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_update_cursor() 315 power_domain = POWER_DOMAIN_PIPE(PIPE_A); in i845_cursor_get_hw_state() 320 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; in i845_cursor_get_hw_state() 322 *pipe = PIPE_A; in i845_cursor_get_hw_state()
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A D | g4x_dp.c | 285 *pipe = PIPE_A; in cpt_dp_port_selected() 462 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down() 463 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down() 467 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down() 476 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_dp_link_down() 477 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down() 478 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down() 1393 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
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A D | intel_crt.c | 242 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_disable_crt() 271 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_post_disable_crt() 283 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_pre_pll_enable_crt() 328 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_enable_crt() 1049 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init() 1115 FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
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A D | intel_pipe_crc.c | 180 case PIPE_A: in vlv_pipe_crc_ctl_reg() 244 case PIPE_A: in vlv_undo_pipe_scramble_reset() 317 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
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A D | intel_fifo_underrun.c | 136 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting() 223 u32 bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
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A D | intel_dpll.c | 1141 if (crtc->pipe != PIPE_A) in vlv_compute_dpll() 1159 if (crtc->pipe != PIPE_A) in chv_compute_dpll() 1573 if (pipe == PIPE_A) in vlv_prepare_pll() 1581 if (pipe == PIPE_A) in vlv_prepare_pll() 1786 if (pipe != PIPE_A) { in chv_enable_pll() 1860 if (pipe != PIPE_A) in vlv_disable_pll() 1877 if (pipe != PIPE_A) in chv_disable_pll()
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A D | intel_ddi.c | 475 case PIPE_A: in intel_ddi_transcoder_func_reg_val_get() 754 *pipe_mask = BIT(PIPE_A); in intel_ddi_get_encoder_pipes() 2217 return BIT(PIPE_A) | BIT(PIPE_B); in intel_ddi_splitter_pipe_mask() 2219 return BIT(PIPE_A); in intel_ddi_splitter_pipe_mask() 2883 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_post_disable() 2885 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); in intel_ddi_fdi_post_disable() 2890 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); in intel_ddi_fdi_post_disable() 2895 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_post_disable() 2897 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); in intel_ddi_fdi_post_disable() 2899 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_post_disable() [all …]
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A D | intel_pps.c | 126 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps() 183 pipe = PIPE_A; in vlv_power_sequencer_pipe() 260 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe() 956 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
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A D | intel_vdsc.c | 352 (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP || in intel_dsc_source_support() 373 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); in is_pipe_dsc() 564 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) in intel_dsc_power_domain()
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A D | intel_display.h | 87 PIPE_A = 0, enumerator 106 TRANSCODER_A = PIPE_A,
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A D | intel_display_power.c | 1264 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable() 1273 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable() 1279 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled() 1422 if (pipe != PIPE_A) in vlv_display_power_well_init() 1647 pipe = PIPE_A; in chv_dpio_cmn_power_well_enable() 1711 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable() 1737 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate() 1866 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled() 1897 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well() 4697 .hsw.irq_pipe_mask = BIT(PIPE_A), [all …]
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A D | intel_sdvo.c | 1795 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo() 1796 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo() 1799 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_sdvo() 1805 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_sdvo() 1806 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo() 1807 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
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A D | intel_display.c | 639 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder() 641 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder() 718 return PIPE_A; in intel_crtc_pch_transcoder() 1670 assert_pch_transcoder_disabled(dev_priv, PIPE_A); in lpt_pch_enable() 1675 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); in lpt_pch_enable() 3470 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); in intel_crtc_supports_double_wide() 5236 trans_pipe = PIPE_A; in hsw_enabled_transcoders() 5408 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_get_ddi_port_state() 11484 enum pipe pipe = PIPE_A; in readout_plane_state() 11795 val |= SDVO_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_hdmi_port() [all …]
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/linux/drivers/video/fbdev/intelfb/ |
A D | intelfbhw.c | 482 if (unlikely(pipe == PIPE_A)) in intelfbhw_active_pipe() 483 return PIPE_A; in intelfbhw_active_pipe() 488 if (likely(pipe == PIPE_A)) in intelfbhw_active_pipe() 489 return PIPE_A; in intelfbhw_active_pipe() 494 pipe = PIPE_A; in intelfbhw_active_pipe() 503 u32 palette_reg = (dinfo->pipe == PIPE_A) ? in intelfbhw_setcolreg()
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A D | intelfbhw.h | 182 #define PIPE_A 0 macro
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