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Searched refs:PIPE_B (Results 1 – 25 of 34) sorted by relevance

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/linux/drivers/gpu/drm/i915/gvt/
A Dhandlers.c2286 MMIO_D(PIPEDSL(PIPE_B), D_ALL); in init_generic_mmio_info()
2311 MMIO_D(CURCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
2315 MMIO_D(CURPOS(PIPE_B), D_ALL); in init_generic_mmio_info()
2319 MMIO_D(CURBASE(PIPE_B), D_ALL); in init_generic_mmio_info()
2346 MMIO_D(DSPCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
2347 MMIO_D(DSPADDR(PIPE_B), D_ALL); in init_generic_mmio_info()
2349 MMIO_D(DSPPOS(PIPE_B), D_ALL); in init_generic_mmio_info()
2350 MMIO_D(DSPSIZE(PIPE_B), D_ALL); in init_generic_mmio_info()
2383 MMIO_D(SPRCTL(PIPE_B), D_ALL); in init_generic_mmio_info()
2386 MMIO_D(SPRPOS(PIPE_B), D_ALL); in init_generic_mmio_info()
[all …]
A Dreg.h74 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
83 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
A Ddisplay.c49 pipe = PIPE_B; in get_edp_pipe()
624 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
A Dinterrupt.c454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
A Dcmd_parser.c1286 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1288 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1344 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
1358 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
/linux/drivers/gpu/drm/i915/
A Di915_pci.c103 [PIPE_B] = CURSOR_B_OFFSET, \
109 [PIPE_B] = CURSOR_B_OFFSET, \
116 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
123 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
160 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
223 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
313 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
366 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
396 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
511 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
[all …]
A Dintel_pm.c517 case PIPE_B: in vlv_get_fifo_size()
2061 case PIPE_B: in vlv_atomic_update_fifo()
4434 [PIPE_B] = BIT(DBUF_S1),
4441 [PIPE_B] = BIT(DBUF_S2),
4460 [PIPE_B] = BIT(DBUF_S1),
4468 [PIPE_B] = BIT(DBUF_S1),
4504 [PIPE_B] = BIT(DBUF_S1),
4523 [PIPE_B] = BIT(DBUF_S1),
4531 [PIPE_B] = BIT(DBUF_S1),
4551 [PIPE_B] = BIT(DBUF_S1),
[all …]
A Dintel_device_info.c273 runtime->num_scalers[PIPE_B] = 2; in intel_device_info_runtime_init()
299 runtime->num_sprites[PIPE_B] = 2; in intel_device_info_runtime_init()
344 info->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
A Di915_reg.h4746 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11744 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11758 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12762 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12765 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12768 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12771 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12787 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12790 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12793 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
A Di915_trace.h46 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
73 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
170 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
A Di915_irq.c611 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
1461 case PIPE_B: in i9xx_pipestat_irq_ack()
1896 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
2414 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
3958 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4137 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4258 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/linux/drivers/gpu/drm/i915/display/
A Dintel_dpio_phy.c815 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
827 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
848 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
857 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
870 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
980 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
A Dintel_pipe_crc.c183 case PIPE_B: in vlv_pipe_crc_ctl_reg()
247 case PIPE_B: in vlv_undo_pipe_scramble_reset()
A Dintel_fdi.c157 case PIPE_B: in ilk_check_fdi_lanes()
182 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); in ilk_check_fdi_lanes()
284 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
308 case PIPE_B: in ivb_update_fdi_bc_bifurcation()
A Dintel_display_power.c1266 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
1272 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
1712 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
3248 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3449 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3531 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3750 .hsw.irq_pipe_mask = BIT(PIPE_B),
4068 .hsw.irq_pipe_mask = BIT(PIPE_B),
4392 .hsw.irq_pipe_mask = BIT(PIPE_B),
4537 .hsw.irq_pipe_mask = BIT(PIPE_B),
[all …]
A Dg4x_hdmi.c318 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
596 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
A Dintel_display.h88 PIPE_B, enumerator
107 TRANSCODER_B = PIPE_B,
A Dintel_pps.c126 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
260 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
956 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
A Dicl_dsi.c846 case PIPE_B: in gen11_dsi_configure_transcoder()
1247 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) in icl_apply_kvmr_pipe_a_wa()
1593 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && in gen11_dsi_sync_state()
1734 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
A Di9xx_plane.c896 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_primary_plane_create()
1000 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && in i9xx_get_initial_plane_config()
A Dintel_sprite.c457 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_update_plane()
1772 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
1823 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
A Dvlv_dsi.c1055 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
1080 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1891 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
A Dg4x_dp.c457 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { in intel_dp_link_down()
1393 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
A Dintel_dpll.c1530 if (pipe == PIPE_B) in vlv_prepare_pll()
1794 intel_de_write(dev_priv, DPLL_MD(PIPE_B), in chv_enable_pll()
1804 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll()
/linux/drivers/video/fbdev/intelfb/
A Dintelfbhw.h183 #define PIPE_B 1 macro

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