/linux/drivers/gpu/drm/i915/gvt/ |
A D | handlers.c | 2287 MMIO_D(PIPEDSL(PIPE_C), D_ALL); in init_generic_mmio_info() 2312 MMIO_D(CURCNTR(PIPE_C), D_ALL); in init_generic_mmio_info() 2316 MMIO_D(CURPOS(PIPE_C), D_ALL); in init_generic_mmio_info() 2320 MMIO_D(CURBASE(PIPE_C), D_ALL); in init_generic_mmio_info() 2357 MMIO_D(DSPCNTR(PIPE_C), D_ALL); in init_generic_mmio_info() 2358 MMIO_D(DSPADDR(PIPE_C), D_ALL); in init_generic_mmio_info() 2360 MMIO_D(DSPPOS(PIPE_C), D_ALL); in init_generic_mmio_info() 2361 MMIO_D(DSPSIZE(PIPE_C), D_ALL); in init_generic_mmio_info() 2398 MMIO_D(SPRCTL(PIPE_C), D_ALL); in init_generic_mmio_info() 2401 MMIO_D(SPRPOS(PIPE_C), D_ALL); in init_generic_mmio_info() [all …]
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A D | reg.h | 76 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \ 84 (((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
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A D | display.c | 52 pipe = PIPE_C; in get_edp_pipe() 625 [PIPE_C] = PIPE_C_VBLANK, in emulate_vblank_on_pipe() 629 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
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A D | interrupt.c | 455 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
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A D | cmd_parser.c | 1289 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, in gen8_decode_mi_display_flip() 1290 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, in gen8_decode_mi_display_flip() 1348 info->pipe = PIPE_C; in skl_decode_mi_display_flip() 1363 info->pipe = PIPE_C; in skl_decode_mi_display_flip()
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/linux/drivers/gpu/drm/i915/ |
A D | i915_pci.c | 110 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 117 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 124 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 447 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 606 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 684 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 846 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 883 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 904 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 916 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), [all …]
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A D | intel_pm.c | 523 case PIPE_C: in vlv_get_fifo_size() 2078 case PIPE_C: in vlv_atomic_update_fifo() 4447 [PIPE_C] = BIT(DBUF_S2), 4454 [PIPE_C] = BIT(DBUF_S2), 4461 [PIPE_C] = BIT(DBUF_S2), 4469 [PIPE_C] = BIT(DBUF_S2), 4517 [PIPE_C] = BIT(DBUF_S2), 4524 [PIPE_C] = BIT(DBUF_S2), 4532 [PIPE_C] = BIT(DBUF_S2), 4566 [PIPE_C] = BIT(DBUF_S1), [all …]
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A D | intel_device_info.c | 274 runtime->num_scalers[PIPE_C] = 1; in intel_device_info_runtime_init() 300 runtime->num_sprites[PIPE_C] = 1; in intel_device_info_runtime_init() 333 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init() 348 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
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A D | i915_trace.h | 47 __entry->frame[PIPE_C], __entry->scanline[PIPE_C]) 74 __entry->frame[PIPE_C], __entry->scanline[PIPE_C]) 171 __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
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A D | i915_irq.c | 1464 case PIPE_C: in i9xx_pipestat_irq_ack() 2417 pipe = PIPE_C; in gen11_dsi_te_interrupt_handler()
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/linux/drivers/gpu/drm/i915/display/ |
A D | intel_pipe_crc.c | 186 case PIPE_C: in vlv_pipe_crc_ctl_reg() 250 case PIPE_C: in vlv_undo_pipe_scramble_reset()
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A D | intel_fdi.c | 161 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); in ilk_check_fdi_lanes() 174 case PIPE_C: in ilk_check_fdi_lanes() 287 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & in cpt_set_fdi_bc_bifurcation() 315 case PIPE_C: in ivb_update_fdi_bc_bifurcation()
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A D | intel_display.h | 89 PIPE_C, enumerator 108 TRANSCODER_C = PIPE_C,
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A D | intel_display_power.c | 1650 pipe = PIPE_C; in chv_dpio_cmn_power_well_enable() 1715 assert_pll_disabled(dev_priv, PIPE_C); in chv_dpio_cmn_power_well_disable() 3248 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 3449 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 3531 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 3591 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 3932 .hsw.irq_pipe_mask = BIT(PIPE_C), 4340 .hsw.irq_pipe_mask = BIT(PIPE_C), 4406 .hsw.irq_pipe_mask = BIT(PIPE_C), 4633 .hsw.irq_pipe_mask = BIT(PIPE_C), [all …]
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A D | skl_universal_plane.c | 1822 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) in skl_plane_has_planar() 1883 return pipe != PIPE_C; in skl_plane_has_ccs() 1885 return pipe != PIPE_C && in skl_plane_has_ccs()
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A D | g4x_hdmi.c | 594 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
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A D | intel_cursor.c | 479 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && in i9xx_check_cursor()
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A D | icl_dsi.c | 849 case PIPE_C: in gen11_dsi_configure_transcoder() 1737 *pipe = PIPE_C; in gen11_dsi_get_hw_state()
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A D | intel_display_types.h | 1754 case PIPE_C: in vlv_pipe_to_channel()
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A D | g4x_dp.c | 1391 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
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A D | vlv_dsi.c | 1075 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
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A D | intel_ddi.c | 488 case PIPE_C: in intel_ddi_transcoder_func_reg_val_get() 760 *pipe_mask = BIT(PIPE_C); in intel_ddi_get_encoder_pipes()
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A D | intel_display.c | 3899 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_transcoder_timings() 5242 trans_pipe = PIPE_C; in hsw_enabled_transcoders()
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