Searched refs:PLL4 (Results 1 – 14 of 14) sorted by relevance
| /linux/Documentation/devicetree/bindings/sound/ |
| A D | ti,j721e-cpb-audio.yaml | 19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
25 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
34 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
|
| A D | ti,j721e-cpb-ivi-audio.yaml | 24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
31 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
|
| /linux/include/dt-bindings/clock/ |
| A D | qcom,lcc-ipq806x.h | 9 #define PLL4 0 macro
|
| A D | qcom,lcc-mdm9615.h | 11 #define PLL4 0 macro
|
| A D | qcom,lcc-msm8960.h | 9 #define PLL4 0 macro
|
| A D | stm32mp1-clks.h | 186 #define PLL4 179 macro
|
| /linux/arch/arm/boot/dts/ |
| A D | stm32mp157c-odyssey.dts | 41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
|
| /linux/drivers/clk/qcom/ |
| A D | lcc-ipq806x.c | 394 [PLL4] = &pll4.clkr,
|
| A D | lcc-mdm9615.c | 481 [PLL4] = &pll4.clkr,
|
| A D | lcc-msm8960.c | 479 [PLL4] = &pll4.clkr,
|
| /linux/drivers/net/wireless/ath/ath9k/ |
| A D | reg.h | 1377 #define PLL4 0x1618c macro
|
| A D | hw.c | 744 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9003_get_pll_sqsum_dvc()
|
| /linux/arch/arm64/boot/dts/ti/ |
| A D | k3-am65-main.dtsi | 849 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
|
| /linux/drivers/clk/ |
| A D | clk-stm32mp1.c | 1748 PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
|
Completed in 49 milliseconds