| /linux/include/dt-bindings/clock/ |
| A D | rk3036-cru.h | 12 #define PLL_DPLL 2 macro
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| A D | rk3188-cru-common.h | 12 #define PLL_DPLL 2 macro
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| A D | rk3128-cru.h | 12 #define PLL_DPLL 2 macro
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| A D | rk3228-cru.h | 12 #define PLL_DPLL 2 macro
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| A D | rv1108-cru.h | 12 #define PLL_DPLL 1 macro
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| A D | px30-cru.h | 8 #define PLL_DPLL 2 macro
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| A D | rk3288-cru.h | 12 #define PLL_DPLL 2 macro
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| A D | rk3308-cru.h | 12 #define PLL_DPLL 2 macro
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| A D | rk3328-cru.h | 12 #define PLL_DPLL 2 macro
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| A D | rk3368-cru.h | 12 #define PLL_DPLL 3 macro
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| A D | rk3399-cru.h | 13 #define PLL_DPLL 3 macro
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| A D | rk3568-cru.h | 71 #define PLL_DPLL 2 macro
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| /linux/drivers/clk/rockchip/ |
| A D | clk-rk3188.c | 218 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
229 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
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| A D | clk-rk3036.c | 139 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
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| A D | clk-rk3128.c | 161 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
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| A D | clk-rk3228.c | 171 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),
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| A D | clk-rk3328.c | 218 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
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| A D | clk-rv1108.c | 156 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
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| A D | clk-rk3368.c | 134 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
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| A D | clk-rk3288.c | 228 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
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| A D | clk-px30.c | 188 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
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| A D | clk-rk3308.c | 183 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
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| A D | clk-rk3399.c | 223 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
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| A D | clk-rk3568.c | 318 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
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| /linux/arch/arm/boot/dts/ |
| A D | rk3036.dtsi | 242 assigned-clock-parents = <&cru PLL_DPLL>;
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