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Searched refs:PMC (Results 1 – 25 of 50) sorted by relevance

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/linux/drivers/video/fbdev/riva/
A Dnvreg.h126 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
127 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
128 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
129 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
130 #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
131 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
133 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
134 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
135 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
136 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
[all …]
A Dnv_driver.c167 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_memlen()
168 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { in riva_get_memlen()
281 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_maxdclk()
282 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) { in riva_get_maxdclk()
330 par->riva.PMC = in riva_common_setup()
A Driva_hw.c1379 LOAD_FIXED_STATE(Riva,PMC); in LoadStateExt()
1533 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1534 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1535 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1536 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1537 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1538 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1539 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1691 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
2079 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) in nv10GetConfig()
[all …]
/linux/Documentation/firmware-guide/acpi/
A Dintel-pmc-mux.rst10 North Mux-Agent is a function of the Intel PMC firmware that is supported on
11 most Intel based platforms that have the PMC microcontroller. It's used for
16 The North Mux-Agent (aka. Intel PMC Mux Control, or just mux-agent) driver
17 communicates with the PMC microcontroller by using the PMC IPC method
31 is a separate child node under the PMC mux-agent device node. Those nodes do not
35 Scope (_SB.PCI0.PMC.MUX)
54 Scope (_SB.PCI0.PMC.MUX)
73 In order to configure the muxes behind a USB Type-C connector, the PMC firmware
80 the PMC::
117 Scope (_SB.PCI0.PMC)
/linux/Documentation/devicetree/bindings/powerpc/fsl/
A Dpmc.txt6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
8 whose PMC is compatible, and implies deep-sleep capability.
10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
12 whose PMC is compatible, and implies deep-sleep capability.
14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
23 is the PMC block, and the second resource is the Clock Configuration
30 resource is the PMC block interrupt.
/linux/drivers/usb/typec/mux/
A DKconfig13 tristate "Intel PMC mux control"
18 Driver for USB muxes controlled by Intel PMC FW. Intel PMC FW can
/linux/Documentation/ABI/obsolete/
A Dsysfs-driver-intel_pmc_bxt1 These files allow sending arbitrary IPC commands to the PMC/SCU which
10 IPC command to the PMC/SCU.
20 Northpeak through the PMC/SCU.
/linux/drivers/platform/x86/intel/pmc/
A DKconfig7 tristate "Intel PMC Core driver"
15 tasks in the PMC in order to enable transition into the SLPS0 state.
25 - PMC quirks as needed to enable SLPS0/S0ix
/linux/Documentation/devicetree/bindings/arm/tegra/
A Dnvidia,tegra20-pmc.yaml7 title: Tegra Power Management Controller (PMC)
46 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
47 PMC also has blink control which allows 32Khz clock output to
49 Consumer of PMC clock should specify the desired clock by having
51 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
66 signal is fed into the PMC. This signal is optionally inverted, and
67 then fed into the ARM GIC. The PMC is not involved in the detection
85 CPU power good signal from external PMIC to PMC is enabled.
175 by the Tegra PMC.
217 Must contain an entry for each clock required by the PMC
[all …]
A Dnvidia,tegra186-pmc.txt1 NVIDIA Tegra Power Management Controller (PMC)
45 The pin grouping is a fixed attribute of the hardware. The PMC can be
/linux/Documentation/driver-api/xilinx/
A Deemi.rst10 used by any driver to communicate with PMC(Platform Management Controller).
16 device to communicate with a power management controller (PMC) on a
19 Any driver who wants to communicate with PMC using EEMI APIs use the
/linux/drivers/video/fbdev/nvidia/
A Dnv_hw.c147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
164 pll = NV_RD32(par->PMC, 0x4004); in nvGetClocks()
1266 NV_WR32(par->PMC, 0x1700, in NVLoadStateExt()
1270 NV_WR32(par->PMC, 0x170C, in NVLoadStateExt()
1525 NV_WR32(par->PMC, 0x8704, 1); in NVLoadStateExt()
1526 NV_WR32(par->PMC, 0x8140, 0); in NVLoadStateExt()
1527 NV_WR32(par->PMC, 0x8920, 0); in NVLoadStateExt()
1528 NV_WR32(par->PMC, 0x8924, 0); in NVLoadStateExt()
[all …]
A Dnv_backlight.c63 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF; in nvidia_bl_update_status()
76 NV_WR32(par->PMC, 0x10F0, tmp_pmc); in nvidia_bl_update_status()
A Dnv_setup.c234 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) { in nv10GetConfig()
235 NV_WR32(par->PMC, 0x0004, 0x01000001); in nv10GetConfig()
303 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
/linux/Documentation/devicetree/bindings/clock/
A Dvt8500.txt16 - reg : shall be the control register offset from PMC base for the pll clock.
36 - enable-reg : shall be the register offset from PMC base for the enable
44 - divisor-reg : shall be the register offset from PMC base for the divisor
A Dat91-clock.txt31 Power Management Controller (PMC):
/linux/Documentation/devicetree/bindings/thermal/
A Dnvidia,tegra30-tsensor.yaml25 Generates a signal to the PMC when the temperature reaches dangerously high
26 levels to reset the chip and sets a flag in the PMC.
/linux/drivers/pinctrl/renesas/
A Dpinctrl-rzg2l.c86 #define PMC(n) (0x0200 + 0x10 + (n)) macro
154 reg = readb(pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
155 writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
171 reg = readb(pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
172 writeb(reg | BIT(pin), pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
666 reg8 = readb(pctrl->base + PMC(port)); in rzg2l_gpio_request()
668 writeb(reg8, pctrl->base + PMC(port)); in rzg2l_gpio_request()
698 if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { in rzg2l_gpio_get_direction()
/linux/drivers/platform/mellanox/
A DKconfig77 Say y here to enable PMC support. The PMC driver provides access
/linux/arch/powerpc/boot/dts/
A Dxpedite5200_xmon.dts17 form-factor = "PMC/XMC";
108 * 6: PMC monarch indicator
109 * 7: PMC EREADY
445 /* PMC interface */
A Dmvme5100.dts130 /* IDSEL 16 - PMC Slot 1 */
136 /* IDSEL 17 - PMC Slot 2 */
A Dxpedite5200.dts104 * 6: PMC monarch indicator
105 * 7: PMC EREADY
442 /* PMC interface */
/linux/arch/sparc/include/asm/
A Dns87303.h20 #define PMC 0x06 macro
/linux/Documentation/ABI/testing/
A Dsysfs-platform-intel-pmc13 Display global reset setting bits for PMC.
/linux/Documentation/devicetree/bindings/mfd/
A Datmel-flexcom.txt11 - clocks: Should be the Flexcom peripheral clock from PMC.

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