1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (c) 2014-2015 Hisilicon Limited.
4  */
5 
6 #ifndef _HNS_DSAF_PPE_H
7 #define _HNS_DSAF_PPE_H
8 
9 #include <linux/platform_device.h>
10 
11 #include "hns_dsaf_main.h"
12 #include "hns_dsaf_mac.h"
13 #include "hns_dsaf_rcb.h"
14 
15 #define HNS_PPE_SERVICE_NW_ENGINE_NUM DSAF_COMM_CHN
16 #define HNS_PPE_DEBUG_NW_ENGINE_NUM 1
17 #define HNS_PPE_COM_NUM DSAF_COMM_DEV_NUM
18 
19 #define PPE_COMMON_REG_OFFSET 0x70000
20 #define PPE_REG_OFFSET 0x10000
21 
22 #define ETH_PPE_DUMP_NUM 576
23 #define ETH_PPE_STATIC_NUM 12
24 
25 #define HNS_PPEV2_RSS_IND_TBL_SIZE 256
26 #define HNS_PPEV2_RSS_KEY_SIZE 40 /* in bytes or 320 bits */
27 #define HNS_PPEV2_RSS_KEY_NUM (HNS_PPEV2_RSS_KEY_SIZE / sizeof(u32))
28 
29 #define HNS_PPEV2_MAX_FRAME_LEN 0X980
30 
31 enum ppe_qid_mode {
32 	PPE_QID_MODE0 = 0, /* fixed queue id mode */
33 	PPE_QID_MODE1,	   /* switch:128VM non switch:6Port/4VM/4TC */
34 	PPE_QID_MODE2,	   /* switch:32VM/4TC non switch:6Port/16VM */
35 	PPE_QID_MODE3,	   /* switch:4TC/8RSS non switch:2Port/64VM */
36 	PPE_QID_MODE4,	   /* switch:8VM/16RSS non switch:2Port/16VM/4TC */
37 	PPE_QID_MODE5,	   /* switch:16VM/8TC non switch:6Port/16RSS */
38 	PPE_QID_MODE6,	   /* switch:32VM/4RSS non switch:6Port/2VM/8TC */
39 	PPE_QID_MODE7,	   /* switch:32RSS non switch:2Port/8VM/8TC */
40 	PPE_QID_MODE8,	   /* switch:6VM/4TC/4RSS non switch:2Port/16VM/4RSS */
41 	PPE_QID_MODE9,	   /* non switch:2Port/32VM/2RSS */
42 	PPE_QID_MODE10,	   /* non switch:2Port/32RSS */
43 	PPE_QID_MODE11,	   /* non switch:2Port/4TC/16RSS */
44 };
45 
46 enum ppe_port_mode {
47 	PPE_MODE_GE = 0,
48 	PPE_MODE_XGE,
49 };
50 
51 enum ppe_common_mode {
52 	PPE_COMMON_MODE_DEBUG = 0,
53 	PPE_COMMON_MODE_SERVICE,
54 	PPE_COMMON_MODE_MAX
55 };
56 
57 struct hns_ppe_hw_stats {
58 	u64 rx_pkts_from_sw;
59 	u64 rx_pkts;
60 	u64 rx_drop_no_bd;
61 	u64 rx_alloc_buf_fail;
62 	u64 rx_alloc_buf_wait;
63 	u64 rx_drop_no_buf;
64 	u64 rx_err_fifo_full;
65 	u64 tx_bd_form_rcb;
66 	u64 tx_pkts_from_rcb;
67 	u64 tx_pkts;
68 	u64 tx_err_fifo_empty;
69 	u64 tx_err_checksum;
70 };
71 
72 struct hns_ppe_cb {
73 	struct device *dev;
74 	struct hns_ppe_cb *next;	/* pointer to next ppe device */
75 	struct ppe_common_cb *ppe_common_cb; /* belong to */
76 	struct hns_ppe_hw_stats hw_stats;
77 
78 	u8 index;	/* index in a ppe common device */
79 	u8 __iomem *io_base;
80 	int virq;
81 	u32 rss_indir_table[HNS_PPEV2_RSS_IND_TBL_SIZE]; /*shadow indir tab */
82 	u32 rss_key[HNS_PPEV2_RSS_KEY_NUM]; /* rss hash key */
83 };
84 
85 struct ppe_common_cb {
86 	struct device *dev;
87 	struct dsaf_device *dsaf_dev;
88 	u8 __iomem *io_base;
89 
90 	enum ppe_common_mode ppe_mode;
91 
92 	u8 comm_index;   /*ppe_common index*/
93 
94 	u32 ppe_num;
95 	struct hns_ppe_cb ppe_cb[];
96 
97 };
98 
99 int hns_ppe_wait_tx_fifo_clean(struct hns_ppe_cb *ppe_cb);
100 int hns_ppe_init(struct dsaf_device *dsaf_dev);
101 
102 void hns_ppe_uninit(struct dsaf_device *dsaf_dev);
103 
104 void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index);
105 
106 void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb);
107 
108 int hns_ppe_get_sset_count(int stringset);
109 int hns_ppe_get_regs_count(void);
110 void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data);
111 
112 void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data);
113 void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data);
114 void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value);
115 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
116 			 const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM]);
117 void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
118 			     const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE]);
119 #endif /* _HNS_DSAF_PPE_H */
120