1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ 14 #define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ 15 16 /* 17 ***************************************** 18 * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) 19 ***************************************** 20 */ 21 22 /* PSOC_GLOBAL_CONF_NON_RST_FLOPS */ 23 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF 25 26 /* PSOC_GLOBAL_CONF_PCI_FW_FSM */ 27 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 29 30 /* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */ 31 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 33 34 /* PSOC_GLOBAL_CONF_BTM_FSM */ 35 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 36 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF 37 38 /* PSOC_GLOBAL_CONF_SW_BTM_FSM */ 39 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 40 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF 41 42 /* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */ 43 #define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0 44 #define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0xF 45 46 /* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */ 47 #define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0 48 #define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF 49 50 /* PSOC_GLOBAL_CONF_SPI_MEM_EN */ 51 #define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT 0 52 #define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK 0x1 53 54 /* PSOC_GLOBAL_CONF_PRSTN */ 55 #define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0 56 #define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1 57 58 /* PSOC_GLOBAL_CONF_PCIE_EN */ 59 #define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0 60 #define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1 61 62 /* PSOC_GLOBAL_CONF_SPI_IMG_STS */ 63 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT 0 64 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK 0x1 65 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT 1 66 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK 0x2 67 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT 2 68 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK 0x4 69 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT 3 70 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK 0x8 71 72 /* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */ 73 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0 74 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1 75 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1 76 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2 77 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2 78 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4 79 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3 80 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8 81 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4 82 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10 83 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5 84 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20 85 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6 86 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40 87 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7 88 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80 89 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8 90 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100 91 92 /* PSOC_GLOBAL_CONF_SCRATCHPAD */ 93 #define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0 94 #define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF 95 96 /* PSOC_GLOBAL_CONF_SEMAPHORE */ 97 #define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0 98 #define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF 99 100 /* PSOC_GLOBAL_CONF_WARM_REBOOT */ 101 #define PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_SHIFT 0 102 #define PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_MASK 0xFFFFFFFF 103 104 /* PSOC_GLOBAL_CONF_UBOOT_MAGIC */ 105 #define PSOC_GLOBAL_CONF_UBOOT_MAGIC_VAL_SHIFT 0 106 #define PSOC_GLOBAL_CONF_UBOOT_MAGIC_VAL_MASK 0xFFFFFFFF 107 108 /* PSOC_GLOBAL_CONF_SPL_SOURCE */ 109 #define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0 110 #define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7 111 112 /* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */ 113 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0 114 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1 115 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1 116 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2 117 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2 118 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4 119 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3 120 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8 121 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4 122 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10 123 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5 124 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20 125 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6 126 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40 127 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7 128 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80 129 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8 130 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100 131 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9 132 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200 133 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10 134 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00 135 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15 136 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000 137 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19 138 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000 139 140 /* PSOC_GLOBAL_CONF_I2C_SLV */ 141 #define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0 142 #define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1 143 144 /* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */ 145 #define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT 0 146 #define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK 0x1 147 148 /* PSOC_GLOBAL_CONF_APP_STATUS */ 149 #define PSOC_GLOBAL_CONF_APP_STATUS_IND_SHIFT 0 150 #define PSOC_GLOBAL_CONF_APP_STATUS_IND_MASK 0xFFFFFFFF 151 152 /* PSOC_GLOBAL_CONF_BTL_STS */ 153 #define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0 154 #define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1 155 #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4 156 #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10 157 #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8 158 #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00 159 160 /* PSOC_GLOBAL_CONF_TIMEOUT_INTR */ 161 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0 162 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1 163 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1 164 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2 165 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2 166 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4 167 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3 168 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8 169 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4 170 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10 171 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5 172 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20 173 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6 174 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40 175 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7 176 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80 177 178 /* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */ 179 #define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0 180 #define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1 181 182 /* PSOC_GLOBAL_CONF_PERIPH_INTR */ 183 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0 184 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1 185 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1 186 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2 187 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2 188 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4 189 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3 190 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8 191 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4 192 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10 193 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5 194 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20 195 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6 196 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40 197 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7 198 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80 199 #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12 200 #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000 201 #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13 202 #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000 203 #define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16 204 #define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000 205 206 /* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */ 207 #define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0 208 #define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1 209 210 /* PSOC_GLOBAL_CONF_AXI_ERR_INTR */ 211 #define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0 212 #define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1 213 214 /* PSOC_GLOBAL_CONF_TARGETID */ 215 #define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1 216 #define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE 217 #define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 12 218 #define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFFF000 219 #define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28 220 #define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000 221 222 /* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */ 223 #define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0 224 #define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1 225 226 /* PSOC_GLOBAL_CONF_MII_ADDR */ 227 #define PSOC_GLOBAL_CONF_MII_ADDR_VAL_SHIFT 0 228 #define PSOC_GLOBAL_CONF_MII_ADDR_VAL_MASK 0xFF 229 230 /* PSOC_GLOBAL_CONF_MII_SPEED */ 231 #define PSOC_GLOBAL_CONF_MII_SPEED_VAL_SHIFT 0 232 #define PSOC_GLOBAL_CONF_MII_SPEED_VAL_MASK 0x3 233 234 /* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */ 235 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT 0 236 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK 0x1 237 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT 1 238 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK 0x2 239 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT 2 240 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK 0x4 241 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT 3 242 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK 0x8 243 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT 4 244 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK 0x10 245 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT 5 246 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK 0xFE0 247 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BOOT_STG2_SRC_SHIFT 12 248 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BOOT_STG2_SRC_MASK 0x3000 249 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_BPS_SHIFT 14 250 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_BPS_MASK 0x1FC000 251 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_SHIFT 21 252 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK 0x200000 253 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_CFG_SHIFT 22 254 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_CFG_MASK 0x1C00000 255 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_MEM_REPAIR_BPS_SHIFT 25 256 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_MEM_REPAIR_BPS_MASK 0x2000000 257 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SPARE_SHIFT 26 258 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SPARE_MASK 0x1C000000 259 260 /* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */ 261 #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0 262 #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1 263 #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT 1 264 #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK 0x2 265 266 /* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */ 267 #define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0 268 #define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1 269 270 /* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */ 271 #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0 272 #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1 273 #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1 274 #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2 275 276 /* PSOC_GLOBAL_CONF_MASK_REQ */ 277 #define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0 278 #define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1 279 280 /* PSOC_GLOBAL_CONF_PRSTN_RST_CFG */ 281 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_SHIFT 0 282 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_MASK 0x1 283 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_IF_SHIFT 1 284 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_IF_MASK 0x2 285 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PLL_SHIFT 2 286 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PLL_MASK 0x1FC 287 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_SHIFT 9 288 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_MASK 0x200 289 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MME_SHIFT 10 290 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MME_MASK 0x400 291 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MC_SHIFT 11 292 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MC_MASK 0x800 293 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_CPU_SHIFT 12 294 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_CPU_MASK 0x1000 295 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_IC_IF_SHIFT 13 296 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_IC_IF_MASK 0x2000 297 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PSOC_SHIFT 14 298 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PSOC_MASK 0x4000 299 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_SRAM_SHIFT 15 300 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_SRAM_MASK 0x1F8000 301 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_SHIFT 21 302 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_MASK 0x200000 303 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_IF_SHIFT 22 304 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_IF_MASK 0x400000 305 306 /* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG */ 307 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_SHIFT 0 308 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_MASK 0x1 309 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_IF_SHIFT 1 310 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_IF_MASK 0x2 311 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PLL_SHIFT 2 312 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PLL_MASK 0x1FC 313 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT 9 314 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_MASK 0x200 315 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT 10 316 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_MASK 0x400 317 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_SHIFT 11 318 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_MASK 0x800 319 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_SHIFT 12 320 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_MASK 0x1000 321 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_SHIFT 13 322 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_MASK 0x2000 323 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_SHIFT 14 324 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_MASK 0x4000 325 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_SHIFT 15 326 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_MASK 0x1F8000 327 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT 21 328 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_MASK 0x200000 329 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_SHIFT 22 330 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_MASK 0x400000 331 332 /* PSOC_GLOBAL_CONF_WD_RST_CFG */ 333 #define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_SHIFT 0 334 #define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_MASK 0x1 335 #define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_IF_SHIFT 1 336 #define PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_IF_MASK 0x2 337 #define PSOC_GLOBAL_CONF_WD_RST_CFG_PLL_SHIFT 2 338 #define PSOC_GLOBAL_CONF_WD_RST_CFG_PLL_MASK 0x1FC 339 #define PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_SHIFT 9 340 #define PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_MASK 0x200 341 #define PSOC_GLOBAL_CONF_WD_RST_CFG_MME_SHIFT 10 342 #define PSOC_GLOBAL_CONF_WD_RST_CFG_MME_MASK 0x400 343 #define PSOC_GLOBAL_CONF_WD_RST_CFG_MC_SHIFT 11 344 #define PSOC_GLOBAL_CONF_WD_RST_CFG_MC_MASK 0x800 345 #define PSOC_GLOBAL_CONF_WD_RST_CFG_CPU_SHIFT 12 346 #define PSOC_GLOBAL_CONF_WD_RST_CFG_CPU_MASK 0x1000 347 #define PSOC_GLOBAL_CONF_WD_RST_CFG_IC_IF_SHIFT 13 348 #define PSOC_GLOBAL_CONF_WD_RST_CFG_IC_IF_MASK 0x2000 349 #define PSOC_GLOBAL_CONF_WD_RST_CFG_PSOC_SHIFT 14 350 #define PSOC_GLOBAL_CONF_WD_RST_CFG_PSOC_MASK 0x4000 351 #define PSOC_GLOBAL_CONF_WD_RST_CFG_SRAM_SHIFT 15 352 #define PSOC_GLOBAL_CONF_WD_RST_CFG_SRAM_MASK 0x1F8000 353 #define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_SHIFT 21 354 #define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_MASK 0x200000 355 #define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_IF_SHIFT 22 356 #define PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_IF_MASK 0x400000 357 358 /* PSOC_GLOBAL_CONF_MNL_RST_CFG */ 359 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_SHIFT 0 360 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_MASK 0x1 361 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_IF_SHIFT 1 362 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_IF_MASK 0x2 363 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_PLL_SHIFT 2 364 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_PLL_MASK 0x1FC 365 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_SHIFT 9 366 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_MASK 0x200 367 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_MME_SHIFT 10 368 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_MME_MASK 0x400 369 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_MC_SHIFT 11 370 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_MC_MASK 0x800 371 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_CPU_SHIFT 12 372 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_CPU_MASK 0x1000 373 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_IC_IF_SHIFT 13 374 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_IC_IF_MASK 0x2000 375 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_PSOC_SHIFT 14 376 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_PSOC_MASK 0x4000 377 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_SRAM_SHIFT 15 378 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_SRAM_MASK 0x1F8000 379 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_SHIFT 21 380 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_MASK 0x200000 381 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_IF_SHIFT 22 382 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_IF_MASK 0x400000 383 384 /* PSOC_GLOBAL_CONF_UNIT_RST_N */ 385 #define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_SHIFT 0 386 #define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_MASK 0x1 387 #define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_IF_SHIFT 1 388 #define PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_IF_MASK 0x2 389 #define PSOC_GLOBAL_CONF_UNIT_RST_N_PLL_SHIFT 2 390 #define PSOC_GLOBAL_CONF_UNIT_RST_N_PLL_MASK 0x1FC 391 #define PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_SHIFT 9 392 #define PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_MASK 0x200 393 #define PSOC_GLOBAL_CONF_UNIT_RST_N_MME_SHIFT 10 394 #define PSOC_GLOBAL_CONF_UNIT_RST_N_MME_MASK 0x400 395 #define PSOC_GLOBAL_CONF_UNIT_RST_N_MC_SHIFT 11 396 #define PSOC_GLOBAL_CONF_UNIT_RST_N_MC_MASK 0x800 397 #define PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_SHIFT 12 398 #define PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_MASK 0x1000 399 #define PSOC_GLOBAL_CONF_UNIT_RST_N_IC_IF_SHIFT 13 400 #define PSOC_GLOBAL_CONF_UNIT_RST_N_IC_IF_MASK 0x2000 401 #define PSOC_GLOBAL_CONF_UNIT_RST_N_PSOC_SHIFT 14 402 #define PSOC_GLOBAL_CONF_UNIT_RST_N_PSOC_MASK 0x4000 403 #define PSOC_GLOBAL_CONF_UNIT_RST_N_SRAM_SHIFT 15 404 #define PSOC_GLOBAL_CONF_UNIT_RST_N_SRAM_MASK 0x1F8000 405 #define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_SHIFT 21 406 #define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_MASK 0x200000 407 #define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_IF_SHIFT 22 408 #define PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_IF_MASK 0x400000 409 410 /* PSOC_GLOBAL_CONF_PRSTN_MASK */ 411 #define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0 412 #define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1 413 414 /* PSOC_GLOBAL_CONF_WD_MASK */ 415 #define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0 416 #define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1 417 418 /* PSOC_GLOBAL_CONF_RST_SRC */ 419 #define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT 0 420 #define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK 0xF 421 422 /* PSOC_GLOBAL_CONF_PAD_1V8_CFG */ 423 #define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0 424 #define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F 425 426 /* PSOC_GLOBAL_CONF_PAD_3V3_CFG */ 427 #define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0 428 #define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F 429 430 /* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */ 431 #define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT 0 432 #define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK 0x7 433 434 /* PSOC_GLOBAL_CONF_BNK3V3_MS */ 435 #define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0 436 #define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3 437 438 /* PSOC_GLOBAL_CONF_PAD_DEFAULT */ 439 #define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0 440 #define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF 441 442 /* PSOC_GLOBAL_CONF_PAD_SEL */ 443 #define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0 444 #define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3 445 446 #endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */ 447