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Searched refs:REG (Results 1 – 25 of 236) sorted by relevance

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/linux/drivers/net/ethernet/mscc/
A Docelot_vsc7514.c24 REG(ANA_ADVLEARN, 0x009000),
25 REG(ANA_VLANMASK, 0x009004),
27 REG(ANA_ANAGEFIL, 0x00900c),
28 REG(ANA_ANEVENTS, 0x009010),
33 REG(ANA_AUTOAGE, 0x009030),
36 REG(ANA_AGENCTRL, 0x00903c),
39 REG(ANA_FLOODING, 0x009048),
174 REG(REW_PPT, 0x000680),
278 REG(DEV_EVENTS, 0x8),
279 REG(DEV_EEE_CFG, 0xc),
[all …]
/linux/tools/perf/arch/csky/util/
A Dunwind-libdw.c15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
22 dwarf_regs[0] = REG(A0); in libdw__arch_set_initial_registers()
23 dwarf_regs[1] = REG(A1); in libdw__arch_set_initial_registers()
24 dwarf_regs[2] = REG(A2); in libdw__arch_set_initial_registers()
25 dwarf_regs[3] = REG(A3); in libdw__arch_set_initial_registers()
36 dwarf_regs[14] = REG(SP); in libdw__arch_set_initial_registers()
37 dwarf_regs[15] = REG(LR); in libdw__arch_set_initial_registers()
54 dwarf_regs[32] = REG(PC); in libdw__arch_set_initial_registers()
56 dwarf_regs[0] = REG(SP); in libdw__arch_set_initial_registers()
58 dwarf_regs[2] = REG(A0); in libdw__arch_set_initial_registers()
[all …]
/linux/drivers/net/dsa/ocelot/
A Dfelix_vsc9959.c22 REG(ANA_ADVLEARN, 0x0089a0),
23 REG(ANA_VLANMASK, 0x0089a4),
25 REG(ANA_ANAGEFIL, 0x0089ac),
26 REG(ANA_ANEVENTS, 0x0089b0),
31 REG(ANA_AUTOAGE, 0x0089d0),
33 REG(ANA_LEARNDISC, 0x0089d8),
34 REG(ANA_AGENCTRL, 0x0089dc),
37 REG(ANA_FLOODING, 0x0089e8),
325 REG(DEV_CLOCK_CFG, 0x0),
327 REG(DEV_EVENTS, 0x8),
[all …]
A Dseville_vsc9953.c23 REG(ANA_ADVLEARN, 0x00b500),
24 REG(ANA_VLANMASK, 0x00b504),
26 REG(ANA_ANAGEFIL, 0x00b50c),
27 REG(ANA_ANEVENTS, 0x00b510),
32 REG(ANA_AUTOAGE, 0x00b530),
34 REG(ANA_LEARNDISC, 0x00b538),
35 REG(ANA_AGENCTRL, 0x00b53c),
38 REG(ANA_FLOODING, 0x00b548),
317 REG(DEV_CLOCK_CFG, 0x0),
318 REG(DEV_PORT_MISC, 0x4),
[all …]
/linux/tools/perf/arch/s390/util/
A Dunwind-libdw.c15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
24 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
25 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
26 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
27 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
28 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
29 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
30 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
31 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
32 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
/linux/tools/perf/arch/arm64/util/
A Dunwind-libdw.c13 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
19 dwarf_regs[0] = REG(X0); in libdw__arch_set_initial_registers()
20 dwarf_regs[1] = REG(X1); in libdw__arch_set_initial_registers()
21 dwarf_regs[2] = REG(X2); in libdw__arch_set_initial_registers()
22 dwarf_regs[3] = REG(X3); in libdw__arch_set_initial_registers()
23 dwarf_regs[4] = REG(X4); in libdw__arch_set_initial_registers()
24 dwarf_regs[5] = REG(X5); in libdw__arch_set_initial_registers()
25 dwarf_regs[6] = REG(X6); in libdw__arch_set_initial_registers()
26 dwarf_regs[7] = REG(X7); in libdw__arch_set_initial_registers()
27 dwarf_regs[8] = REG(X8); in libdw__arch_set_initial_registers()
[all …]
/linux/tools/perf/arch/riscv/util/
A Dunwind-libdw.c15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
22 dwarf_regs[1] = REG(RA); in libdw__arch_set_initial_registers()
23 dwarf_regs[2] = REG(SP); in libdw__arch_set_initial_registers()
24 dwarf_regs[3] = REG(GP); in libdw__arch_set_initial_registers()
25 dwarf_regs[4] = REG(TP); in libdw__arch_set_initial_registers()
26 dwarf_regs[5] = REG(T0); in libdw__arch_set_initial_registers()
27 dwarf_regs[6] = REG(T1); in libdw__arch_set_initial_registers()
28 dwarf_regs[7] = REG(T2); in libdw__arch_set_initial_registers()
29 dwarf_regs[8] = REG(S0); in libdw__arch_set_initial_registers()
30 dwarf_regs[9] = REG(S1); in libdw__arch_set_initial_registers()
[all …]
/linux/tools/perf/arch/powerpc/util/
A Dunwind-libdw.c22 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
28 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
29 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
30 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
31 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
32 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
33 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
34 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
35 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
36 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
/linux/drivers/net/ethernet/apple/
A Dmace.h12 REG(rcvfifo); /* receive FIFO */
13 REG(xmtfifo); /* transmit FIFO */
22 REG(pr); /* poll register */
31 REG(reg19);
34 REG(reg22);
35 REG(reg23);
37 REG(reg25);
40 REG(reg28);
41 REG(utr); /* user test reg */
42 REG(reg30);
[all …]
/linux/drivers/gpu/drm/i915/gt/
A Dintel_lrc.c82 REG(0x034),
83 REG(0x030),
84 REG(0x038),
85 REG(0x03c),
86 REG(0x168),
87 REG(0x140),
88 REG(0x110),
89 REG(0x11c),
90 REG(0x114),
91 REG(0x118),
[all …]
/linux/tools/perf/arch/x86/util/
A Dunwind-libdw.c14 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
21 dwarf_regs[0] = REG(AX); in libdw__arch_set_initial_registers()
22 dwarf_regs[1] = REG(CX); in libdw__arch_set_initial_registers()
23 dwarf_regs[2] = REG(DX); in libdw__arch_set_initial_registers()
24 dwarf_regs[3] = REG(BX); in libdw__arch_set_initial_registers()
25 dwarf_regs[4] = REG(SP); in libdw__arch_set_initial_registers()
26 dwarf_regs[5] = REG(BP); in libdw__arch_set_initial_registers()
27 dwarf_regs[6] = REG(SI); in libdw__arch_set_initial_registers()
28 dwarf_regs[7] = REG(DI); in libdw__arch_set_initial_registers()
29 dwarf_regs[8] = REG(IP); in libdw__arch_set_initial_registers()
[all …]
/linux/drivers/regulator/
A Drn5t618-regulator.c25 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
45 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
46 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
47 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
48 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
50 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
51 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
52 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
53 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
54 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
[all …]
/linux/drivers/gpu/drm/tidss/
A Dtidss_dispc_regs.h55 #define REG(r) (dispc_common_regmap[r ## _OFF]) macro
57 #define DSS_REVISION REG(DSS_REVISION)
58 #define DSS_SYSCONFIG REG(DSS_SYSCONFIG)
59 #define DSS_SYSSTATUS REG(DSS_SYSSTATUS)
60 #define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI)
62 #define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS)
69 #define WB_IRQENABLE REG(WB_IRQENABLE)
70 #define WB_IRQSTATUS REG(WB_IRQSTATUS)
75 #define DSS_CBA_CFG REG(DSS_CBA_CFG)
91 #define DISPC_MSS_VP1 REG(DISPC_MSS_VP1)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
A Dhw_translate_dcn10.c51 #define REG(reg_name)\ macro
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
180 case REG(DC_GPIO_DDC6_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
A Dhw_translate_dce120.c51 #define REG(reg_name)\ macro
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
180 case REG(DC_GPIO_DDC6_A): in offset_to_id()
[all …]
/linux/tools/testing/selftests/powerpc/nx-gzip/include/
A Dnxu.h428 #define getnn(ST, REG) ((be32toh(ST.REG) >> (31-REG##_offset)) \ argument
430 #define getpnn(ST, REG) ((be32toh((ST)->REG) >> (31-REG##_offset)) \ argument
432 #define get32(ST, REG) (be32toh(ST.REG)) argument
433 #define getp32(ST, REG) (be32toh((ST)->REG)) argument
434 #define get64(ST, REG) (be64toh(ST.REG)) argument
435 #define getp64(ST, REG) (be64toh((ST)->REG)) argument
437 #define unget32(ST, REG) (get32(ST, REG) & ~((REG##_mask) \ argument
441 #define ungetp32(ST, REG) (getp32(ST, REG) & ~((REG##_mask) \ argument
452 #define putnn(ST, REG, X) (ST.REG = htobe32(unget32(ST, REG) | (((X) \ argument
453 & REG##_mask) << (31-REG##_offset))))
[all …]
/linux/tools/perf/arch/arm/util/
A Dunwind-libdw.c13 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
19 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
20 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
21 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
22 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
23 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
24 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
25 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
26 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
27 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
/linux/arch/sparc/include/asm/
A Dtrap_block.h120 #define __GET_CPUID(REG) \ argument
123 srlx REG, 17, REG; \
124 and REG, 0x1f, REG; \
131 srlx REG, 17, REG; \
132 and REG, 0x3ff, REG; \
136 srlx REG, 17, REG; \
137 and REG, 0x1f, REG; \
141 sllx REG, 9, REG; \
142 or REG, 0xd0, REG; \
143 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dpp_cm.c42 #define REG(reg)\ macro
135 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); in program_gamut_remap()
136 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); in program_gamut_remap()
145 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in program_gamut_remap()
146 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); in program_gamut_remap()
220 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12); in dpp1_cm_program_color_matrix()
221 gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34); in dpp1_cm_program_color_matrix()
225 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in dpp1_cm_program_color_matrix()
226 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); in dpp1_cm_program_color_matrix()
476 gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12); in dpp1_program_input_csc()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dwb_cm.c36 #define REG(reg)\ macro
104 gam_regs.offset_b = REG(DWB_OGAM_RAMA_OFFSET_B); in dwb3_program_ogam_luta_settings()
105 gam_regs.offset_g = REG(DWB_OGAM_RAMA_OFFSET_G); in dwb3_program_ogam_luta_settings()
106 gam_regs.offset_r = REG(DWB_OGAM_RAMA_OFFSET_R); in dwb3_program_ogam_luta_settings()
107 gam_regs.region_start = REG(DWB_OGAM_RAMA_REGION_0_1); in dwb3_program_ogam_luta_settings()
108 gam_regs.region_end = REG(DWB_OGAM_RAMA_REGION_32_33); in dwb3_program_ogam_luta_settings()
137 gam_regs.offset_b = REG(DWB_OGAM_RAMB_OFFSET_B); in dwb3_program_ogam_lutb_settings()
138 gam_regs.offset_g = REG(DWB_OGAM_RAMB_OFFSET_G); in dwb3_program_ogam_lutb_settings()
139 gam_regs.offset_r = REG(DWB_OGAM_RAMB_OFFSET_R); in dwb3_program_ogam_lutb_settings()
140 gam_regs.region_start = REG(DWB_OGAM_RAMB_REGION_0_1); in dwb3_program_ogam_lutb_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
A Dhw_translate_dcn20.c54 #undef REG
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
154 case REG(DC_GPIO_DDC1_A): in offset_to_id()
157 case REG(DC_GPIO_DDC2_A): in offset_to_id()
160 case REG(DC_GPIO_DDC3_A): in offset_to_id()
163 case REG(DC_GPIO_DDC4_A): in offset_to_id()
166 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
A Dhw_translate_dcn30.c60 #undef REG
61 #define REG(reg_name)\ macro
79 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
109 case REG(DC_GPIO_HPD_A): in offset_to_id()
136 case REG(DC_GPIO_GENLK_A): in offset_to_id()
160 case REG(DC_GPIO_DDC1_A): in offset_to_id()
163 case REG(DC_GPIO_DDC2_A): in offset_to_id()
166 case REG(DC_GPIO_DDC3_A): in offset_to_id()
169 case REG(DC_GPIO_DDC4_A): in offset_to_id()
172 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/arch/m68k/lib/
A Dmulsi3.S67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
76 #define a1 REG (a1)
[all …]
A Dmodsi3.S69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
78 #define a1 REG (a1)
[all …]
A Dumodsi3.S67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
76 #define a1 REG (a1)
[all …]

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