| /linux/arch/hexagon/include/asm/ |
| A D | elf.h | 93 DEST.cs0 = REGS->cs0;\
94 DEST.cs1 = REGS->cs1;\
102 DEST.r0 = REGS->r00; \
103 DEST.r1 = REGS->r01; \
104 DEST.r2 = REGS->r02; \
105 DEST.r3 = REGS->r03; \
106 DEST.r4 = REGS->r04; \
107 DEST.r5 = REGS->r05; \
138 DEST.m0 = REGS->m0; \
139 DEST.m1 = REGS->m1; \
[all …]
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| /linux/arch/arm/probes/ |
| A D | decode-arm.c | 156 REGS(0, NOPC, 0, 0, 0)),
163 REGS(0, 0, 0, 0, NOPC)),
167 REGS(0, NOPC, 0, 0, NOPC)),
312 REGS(ANY, 0, 0, 0, ANY)),
317 REGS(0, ANY, 0, 0, ANY)),
330 REGS(ANY, ANY, 0, 0, ANY)),
366 REGS(0, NOPC, 0, 0, 0)),
389 REGS(ANY, 0, 0, 0, 0)),
394 REGS(0, ANY, 0, 0, 0)),
407 REGS(ANY, ANY, 0, 0, 0)),
[all …]
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| A D | decode-thumb.c | 59 REGS(NOSP, 0, 0, 0, NOSPPC)),
139 REGS(NOSPPC, 0, 0, 0, 0)),
145 REGS(NOPC, 0, 0, 0, 0)),
150 REGS(0, 0, NOSPPC, 0, 0)),
167 REGS(SP, 0, NOPC, 0, 0)),
198 REGS(SP, 0, SP, 0, 0)),
209 REGS(0, 0, NOSPPC, 0, 0)),
225 REGS(0, 0, NOSPPC, 0, 0)),
248 REGS(0, 0, NOSPPC, 0, 0)),
295 REGS(NOPCX, 0, 0, 0, 0)),
[all …]
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| A D | decode.h | 287 #define REGS(r16, r12, r8, r4, r0) \ macro
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| /linux/drivers/gpu/drm/msm/adreno/ |
| A D | a6xx_gpu_state.h | 279 #define REGS(_array, _sel_reg, _sel_val) \ macro
284 REGS(a6xx_registers, 0, 0),
285 REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
286 REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
315 REGS(a6xx_ahb_registers, 0, 0),
319 REGS(a6xx_vbif_registers, 0, 0);
322 REGS(a6xx_gbif_registers, 0, 0);
364 REGS(a6xx_gmu_cx_registers, 0, 0),
365 REGS(a6xx_gmu_cx_rscc_registers, 0, 0),
366 REGS(a6xx_gmu_gx_registers, 0, 0),
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| /linux/drivers/video/fbdev/nvidia/ |
| A D | nv_setup.c | 295 par->PRAMIN = par->REGS + (0x00710000 / 4); in NVCommonSetup()
296 par->PCRTC0 = par->REGS + (0x00600000 / 4); in NVCommonSetup()
297 par->PRAMDAC0 = par->REGS + (0x00680000 / 4); in NVCommonSetup()
298 par->PFB = par->REGS + (0x00100000 / 4); in NVCommonSetup()
299 par->PFIFO = par->REGS + (0x00002000 / 4); in NVCommonSetup()
300 par->PGRAPH = par->REGS + (0x00400000 / 4); in NVCommonSetup()
301 par->PEXTDEV = par->REGS + (0x00101000 / 4); in NVCommonSetup()
302 par->PTIMER = par->REGS + (0x00009000 / 4); in NVCommonSetup()
303 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
304 par->FIFO = par->REGS + (0x00800000 / 4); in NVCommonSetup()
[all …]
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| A D | nv_type.h | 155 volatile u32 __iomem *REGS; member
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| A D | nvidia.c | 1209 id = NV_RD32(par->REGS, 0x1800); in nvidia_get_chipset()
1325 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); in nvidiafb_probe()
1327 if (!par->REGS) { in nvidiafb_probe()
1414 iounmap(par->REGS); in nvidiafb_probe()
1439 iounmap(par->REGS); in nvidiafb_remove()
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| A D | nv_hw.c | 1225 j = NV_RD32(par->REGS, 0x1540) & 0xff; in NVLoadStateExt()
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| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| A D | dmub_reg.h | 43 #define REG(reg) (REGS)->offset.reg
45 #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field
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| A D | dmub_dcn301.c | 36 #define REGS dmub->regs macro
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| A D | dmub_dcn302.c | 36 #define REGS dmub->regs macro
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| A D | dmub_dcn303.c | 18 #define REGS dmub->regs macro
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| A D | dmub_dcn21.c | 36 #define REGS dmub->regs macro
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| A D | dmub_dcn30.c | 37 #define REGS dmub->regs macro
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| A D | dmub_dcn20.c | 37 #define REGS dmub->regs macro
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| A D | dmub_dcn31.c | 36 #define REGS dmub->regs_dcn31 macro
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| /linux/arch/alpha/include/asm/ |
| A D | elf.h | 114 #define ELF_CORE_COPY_REGS(DEST, REGS) \ argument
115 dump_elf_thread(DEST, REGS, current_thread_info());
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | uvd_v3_1.c | 211 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v3_1_set_dcm()
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| A D | uvd_v4_2.c | 635 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v4_2_set_dcm()
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| /linux/drivers/memory/tegra/ |
| A D | tegra210-emc-cc-r21021.c | 33 #define REGS (1 << 30) macro
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| /linux/sound/pci/ali5451/ |
| A D | ali5451.c | 159 struct REGS { struct
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| /linux/kernel/trace/ |
| A D | Kconfig | 39 by default, even without setting the REGS flag in the ftrace_ops.
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| /linux/Documentation/virt/kvm/ |
| A D | api.rst | 6077 certain guest registers without having to call SET/GET_*REGS. Thus we can
6309 without having to call SET/GET_*REGS". This reduces overhead by eliminating
|