1 #ifndef A6XX_GMU_XML
2 #define A6XX_GMU_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-02-18 16:45:44)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2021-02-18 16:45:44)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-02-18 16:45:44)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14386 bytes, from 2021-02-18 16:45:44)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  67699 bytes, from 2021-05-31 20:21:57)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84226 bytes, from 2021-02-18 16:45:44)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 112551 bytes, from 2021-02-18 16:45:44)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 150713 bytes, from 2021-06-10 22:34:02)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 180049 bytes, from 2021-06-02 21:44:19)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-05-21 19:18:08)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-02-18 16:45:44)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-05-27 20:22:36)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-05-27 20:18:13)
24 
25 Copyright (C) 2013-2021 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28 
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36 
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40 
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49 
50 
51 #define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK		0x00800000
52 #define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT		23
A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB(uint32_t val)53 static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB(uint32_t val)
54 {
55 	return ((val) << A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK;
56 }
57 #define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK	0x40000000
58 #define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT	30
A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB(uint32_t val)59 static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB(uint32_t val)
60 {
61 	return ((val) << A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK;
62 }
63 #define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK		0x00400000
64 #define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT		22
A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK(uint32_t val)65 static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK(uint32_t val)
66 {
67 	return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK;
68 }
69 #define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK		0x40000000
70 #define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT		30
A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK(uint32_t val)71 static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK(uint32_t val)
72 {
73 	return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK;
74 }
75 #define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK		0x40000000
76 #define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT		30
A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK(uint32_t val)77 static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK(uint32_t val)
78 {
79 	return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK;
80 }
81 #define A6XX_GMU_OOB_DCVS_SET_MASK__MASK			0x00800000
82 #define A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT			23
A6XX_GMU_OOB_DCVS_SET_MASK(uint32_t val)83 static inline uint32_t A6XX_GMU_OOB_DCVS_SET_MASK(uint32_t val)
84 {
85 	return ((val) << A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_SET_MASK__MASK;
86 }
87 #define A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK			0x80000000
88 #define A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT			31
A6XX_GMU_OOB_DCVS_CHECK_MASK(uint32_t val)89 static inline uint32_t A6XX_GMU_OOB_DCVS_CHECK_MASK(uint32_t val)
90 {
91 	return ((val) << A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK;
92 }
93 #define A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK			0x80000000
94 #define A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT			31
A6XX_GMU_OOB_DCVS_CLEAR_MASK(uint32_t val)95 static inline uint32_t A6XX_GMU_OOB_DCVS_CLEAR_MASK(uint32_t val)
96 {
97 	return ((val) << A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK;
98 }
99 #define A6XX_GMU_OOB_GPU_SET_MASK__MASK				0x00040000
100 #define A6XX_GMU_OOB_GPU_SET_MASK__SHIFT			18
A6XX_GMU_OOB_GPU_SET_MASK(uint32_t val)101 static inline uint32_t A6XX_GMU_OOB_GPU_SET_MASK(uint32_t val)
102 {
103 	return ((val) << A6XX_GMU_OOB_GPU_SET_MASK__SHIFT) & A6XX_GMU_OOB_GPU_SET_MASK__MASK;
104 }
105 #define A6XX_GMU_OOB_GPU_CHECK_MASK__MASK			0x04000000
106 #define A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT			26
A6XX_GMU_OOB_GPU_CHECK_MASK(uint32_t val)107 static inline uint32_t A6XX_GMU_OOB_GPU_CHECK_MASK(uint32_t val)
108 {
109 	return ((val) << A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CHECK_MASK__MASK;
110 }
111 #define A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK			0x04000000
112 #define A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT			26
A6XX_GMU_OOB_GPU_CLEAR_MASK(uint32_t val)113 static inline uint32_t A6XX_GMU_OOB_GPU_CLEAR_MASK(uint32_t val)
114 {
115 	return ((val) << A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK;
116 }
117 #define A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK			0x00020000
118 #define A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT			17
A6XX_GMU_OOB_PERFCNTR_SET_MASK(uint32_t val)119 static inline uint32_t A6XX_GMU_OOB_PERFCNTR_SET_MASK(uint32_t val)
120 {
121 	return ((val) << A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK;
122 }
123 #define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK			0x02000000
124 #define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT			25
A6XX_GMU_OOB_PERFCNTR_CHECK_MASK(uint32_t val)125 static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CHECK_MASK(uint32_t val)
126 {
127 	return ((val) << A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK;
128 }
129 #define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK			0x02000000
130 #define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT			25
A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK(uint32_t val)131 static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK(uint32_t val)
132 {
133 	return ((val) << A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK;
134 }
135 #define A6XX_HFI_IRQ_MSGQ_MASK					0x00000001
136 #define A6XX_HFI_IRQ_DSGQ_MASK__MASK				0x00000002
137 #define A6XX_HFI_IRQ_DSGQ_MASK__SHIFT				1
A6XX_HFI_IRQ_DSGQ_MASK(uint32_t val)138 static inline uint32_t A6XX_HFI_IRQ_DSGQ_MASK(uint32_t val)
139 {
140 	return ((val) << A6XX_HFI_IRQ_DSGQ_MASK__SHIFT) & A6XX_HFI_IRQ_DSGQ_MASK__MASK;
141 }
142 #define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK			0x00000004
143 #define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT			2
A6XX_HFI_IRQ_BLOCKED_MSG_MASK(uint32_t val)144 static inline uint32_t A6XX_HFI_IRQ_BLOCKED_MSG_MASK(uint32_t val)
145 {
146 	return ((val) << A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT) & A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK;
147 }
148 #define A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK			0x00800000
149 #define A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT			23
A6XX_HFI_IRQ_CM3_FAULT_MASK(uint32_t val)150 static inline uint32_t A6XX_HFI_IRQ_CM3_FAULT_MASK(uint32_t val)
151 {
152 	return ((val) << A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT) & A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK;
153 }
154 #define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK				0x007f0000
155 #define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT			16
A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val)156 static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val)
157 {
158 	return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK;
159 }
160 #define A6XX_HFI_IRQ_OOB_MASK__MASK				0xff000000
161 #define A6XX_HFI_IRQ_OOB_MASK__SHIFT				24
A6XX_HFI_IRQ_OOB_MASK(uint32_t val)162 static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val)
163 {
164 	return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK;
165 }
166 #define A6XX_HFI_H2F_IRQ_MASK_BIT				0x00000001
167 #define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL		0x00000080
168 
169 #define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL			0x00000081
170 
171 #define REG_A6XX_GMU_CM3_ITCM_START				0x00000c00
172 
173 #define REG_A6XX_GMU_CM3_DTCM_START				0x00001c00
174 
175 #define REG_A6XX_GMU_NMI_CONTROL_STATUS				0x000023f0
176 
177 #define REG_A6XX_GMU_BOOT_SLUMBER_OPTION			0x000023f8
178 
179 #define REG_A6XX_GMU_GX_VOTE_IDX				0x000023f9
180 
181 #define REG_A6XX_GMU_MX_VOTE_IDX				0x000023fa
182 
183 #define REG_A6XX_GMU_DCVS_ACK_OPTION				0x000023fc
184 
185 #define REG_A6XX_GMU_DCVS_PERF_SETTING				0x000023fd
186 
187 #define REG_A6XX_GMU_DCVS_BW_SETTING				0x000023fe
188 
189 #define REG_A6XX_GMU_DCVS_RETURN				0x000023ff
190 
191 #define REG_A6XX_GMU_ICACHE_CONFIG				0x00004c00
192 
193 #define REG_A6XX_GMU_DCACHE_CONFIG				0x00004c01
194 
195 #define REG_A6XX_GMU_SYS_BUS_CONFIG				0x00004c0f
196 
197 #define REG_A6XX_GMU_CM3_SYSRESET				0x00005000
198 
199 #define REG_A6XX_GMU_CM3_BOOT_CONFIG				0x00005001
200 
201 #define REG_A6XX_GMU_CM3_FW_BUSY				0x0000501a
202 
203 #define REG_A6XX_GMU_CM3_FW_INIT_RESULT				0x0000501c
204 
205 #define REG_A6XX_GMU_CM3_CFG					0x0000502d
206 
207 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE		0x00005040
208 
209 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0		0x00005041
210 
211 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1		0x00005042
212 
213 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L		0x00005044
214 
215 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H		0x00005045
216 
217 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L		0x00005046
218 
219 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H		0x00005047
220 
221 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L		0x00005048
222 
223 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H		0x00005049
224 
225 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L		0x0000504a
226 
227 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H		0x0000504b
228 
229 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L		0x0000504c
230 
231 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H		0x0000504d
232 
233 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L		0x0000504e
234 
235 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H		0x0000504f
236 
237 #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL			0x000050c0
238 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE		0x00000001
239 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE	0x00000002
240 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE	0x00000004
241 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK	0x00003c00
242 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT	10
A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val)243 static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val)
244 {
245 	return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK;
246 }
247 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK	0xffffc000
248 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT	14
A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val)249 static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val)
250 {
251 	return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK;
252 }
253 
254 #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST			0x000050c1
255 
256 #define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST			0x000050c2
257 
258 #define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS			0x000050d0
259 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF	0x00000001
260 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON	0x00000002
261 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF	0x00000004
262 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON	0x00000008
263 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF		0x00000010
264 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE	0x00000020
265 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF	0x00000040
266 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF		0x00000080
267 
268 #define REG_A6XX_GMU_GPU_NAP_CTRL				0x000050e4
269 #define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE			0x00000001
270 #define A6XX_GMU_GPU_NAP_CTRL_SID__MASK				0x000001f0
271 #define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT			4
A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)272 static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
273 {
274 	return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK;
275 }
276 
277 #define REG_A6XX_GMU_RPMH_CTRL					0x000050e8
278 #define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE		0x00000001
279 #define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE			0x00000010
280 #define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE			0x00000100
281 #define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE			0x00000200
282 #define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE			0x00000400
283 #define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE			0x00000800
284 #define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE			0x00001000
285 #define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE			0x00002000
286 #define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE			0x00004000
287 #define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE			0x00008000
288 
289 #define REG_A6XX_GMU_RPMH_HYST_CTRL				0x000050e9
290 
291 #define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE		0x000050ec
292 
293 #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF			0x000050f0
294 
295 #define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF			0x000050f1
296 
297 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG			0x00005100
298 
299 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP			0x00005101
300 
301 #define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE			0x000051f0
302 
303 #define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL				0x00005157
304 
305 #define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS			0x00005158
306 
307 #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L			0x00005088
308 
309 #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H			0x00005089
310 
311 #define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE			0x000050c3
312 
313 #define REG_A6XX_GMU_HFI_CTRL_STATUS				0x00005180
314 
315 #define REG_A6XX_GMU_HFI_VERSION_INFO				0x00005181
316 
317 #define REG_A6XX_GMU_HFI_SFR_ADDR				0x00005182
318 
319 #define REG_A6XX_GMU_HFI_MMAP_ADDR				0x00005183
320 
321 #define REG_A6XX_GMU_HFI_QTBL_INFO				0x00005184
322 
323 #define REG_A6XX_GMU_HFI_QTBL_ADDR				0x00005185
324 
325 #define REG_A6XX_GMU_HFI_CTRL_INIT				0x00005186
326 
327 #define REG_A6XX_GMU_GMU2HOST_INTR_SET				0x00005190
328 
329 #define REG_A6XX_GMU_GMU2HOST_INTR_CLR				0x00005191
330 
331 #define REG_A6XX_GMU_GMU2HOST_INTR_INFO				0x00005192
332 #define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ			0x00000001
333 #define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT			0x00800000
334 
335 #define REG_A6XX_GMU_GMU2HOST_INTR_MASK				0x00005193
336 
337 #define REG_A6XX_GMU_HOST2GMU_INTR_SET				0x00005194
338 
339 #define REG_A6XX_GMU_HOST2GMU_INTR_CLR				0x00005195
340 
341 #define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO			0x00005196
342 
343 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_0				0x00005197
344 
345 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_1				0x00005198
346 
347 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_2				0x00005199
348 
349 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_3				0x0000519a
350 
351 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0			0x0000519b
352 
353 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1			0x0000519c
354 
355 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2			0x0000519d
356 
357 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3			0x0000519e
358 
359 #define REG_A6XX_GMU_GENERAL_1					0x000051c6
360 
361 #define REG_A6XX_GMU_GENERAL_7					0x000051cc
362 
363 #define REG_A6XX_GMU_ISENSE_CTRL				0x0000515d
364 
365 #define REG_A6XX_GPU_CS_ENABLE_REG				0x00008920
366 
367 #define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL			0x0000515d
368 
369 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3		0x00008578
370 
371 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2		0x00008558
372 
373 #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0				0x00008580
374 
375 #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2				0x00027ada
376 
377 #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS			0x0000881a
378 
379 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1		0x00008957
380 
381 #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS			0x0000881a
382 
383 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0		0x0000881d
384 
385 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2		0x0000881f
386 
387 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4		0x00008821
388 
389 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE			0x00008965
390 
391 #define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL				0x0000896d
392 
393 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE			0x00008965
394 
395 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD			0x0000514d
396 
397 #define REG_A6XX_GMU_AO_INTERRUPT_EN				0x00009303
398 
399 #define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR			0x00009304
400 
401 #define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS			0x00009305
402 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE		0x00000001
403 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP		0x00000002
404 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP		0x00000004
405 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR		0x00000008
406 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP		0x00000010
407 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR	0x00000020
408 
409 #define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK			0x00009306
410 
411 #define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL			0x00009309
412 
413 #define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL			0x0000930a
414 
415 #define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL			0x0000930b
416 
417 #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS			0x0000930c
418 #define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB	0x00800000
419 
420 #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2			0x0000930d
421 
422 #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK			0x0000930e
423 
424 #define REG_A6XX_GMU_AO_AHB_FENCE_CTRL				0x00009310
425 
426 #define REG_A6XX_GMU_AHB_FENCE_STATUS				0x00009313
427 
428 #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS			0x00009315
429 
430 #define REG_A6XX_GMU_AO_SPARE_CNTL				0x00009316
431 
432 #define REG_A6XX_GMU_RSCC_CONTROL_REQ				0x00009307
433 
434 #define REG_A6XX_GMU_RSCC_CONTROL_ACK				0x00009308
435 
436 #define REG_A6XX_GMU_AHB_FENCE_RANGE_0				0x00009311
437 
438 #define REG_A6XX_GMU_AHB_FENCE_RANGE_1				0x00009312
439 
440 #define REG_A6XX_GPU_CC_GX_GDSCR				0x00009c03
441 
442 #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC				0x00009d42
443 
444 #define REG_A6XX_GPU_CPR_FSM_CTL				0x0000c001
445 
446 #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0			0x00000004
447 
448 #define REG_A6XX_RSCC_PDC_SEQ_START_ADDR			0x00000008
449 
450 #define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO			0x00000009
451 
452 #define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI			0x0000000a
453 
454 #define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0				0x0000000b
455 
456 #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR			0x0000000d
457 
458 #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA			0x0000000e
459 
460 #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0		0x00000082
461 
462 #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0		0x00000083
463 
464 #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0			0x00000089
465 
466 #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0		0x0000008c
467 
468 #define REG_A6XX_RSCC_OVERRIDE_START_ADDR			0x00000100
469 
470 #define REG_A6XX_RSCC_SEQ_BUSY_DRV0				0x00000101
471 
472 #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0				0x00000180
473 
474 #define REG_A6XX_RSCC_TCS0_DRV0_STATUS				0x00000346
475 
476 #define REG_A6XX_RSCC_TCS1_DRV0_STATUS				0x000003ee
477 
478 #define REG_A6XX_RSCC_TCS2_DRV0_STATUS				0x00000496
479 
480 #define REG_A6XX_RSCC_TCS3_DRV0_STATUS				0x0000053e
481 
482 
483 #endif /* A6XX_GMU_XML */
484