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Searched refs:REG_GET (Results 1 – 25 of 92) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_hubp.c1075 REG_GET(HUBPRET_CONTROL, in hubp2_read_state_common()
1094 REG_GET(BLANK_OFFSET_1, in hubp2_read_state_common()
1097 REG_GET(DST_DIMENSIONS, in hubp2_read_state_common()
1135 REG_GET(NOM_PARAMETERS_4, in hubp2_read_state_common()
1138 REG_GET(NOM_PARAMETERS_5, in hubp2_read_state_common()
1170 REG_GET(NOM_PARAMETERS_6, in hubp2_read_state_common()
1173 REG_GET(NOM_PARAMETERS_7, in hubp2_read_state_common()
1235 REG_GET(HUBP_CLK_CNTL, in hubp2_read_state_common()
1302 REG_GET(HUBPRET_CONTROL, in hubp2_validate_dml_output()
1398 REG_GET(BLANK_OFFSET_1, in hubp2_validate_dml_output()
[all …]
A Ddcn20_stream_encoder.c356 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc2_read_state()
358 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc2_read_state()
359 REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num); in enc2_read_state()
361 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc2_read_state()
362 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc2_read_state()
364 REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable); in enc2_read_state()
365 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc2_read_state()
436 REG_GET(DP_SEC_METADATA_TRANSMISSION, in enc2_stream_encoder_update_dp_info_packets()
570 REG_GET(DIG_FIFO_STATUS, in enc2_get_fifo_cal_average_level()
A Ddcn20_link_encoder.c194 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active); in enc2_fec_is_active()
206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); in link_enc2_read_state()
207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); in link_enc2_read_state()
208 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); in link_enc2_read_state()
209 REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); in link_enc2_read_state()
279 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); in dcn20_link_encoder_get_max_link_cap()
294 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); in dcn20_link_encoder_is_in_alt_mode()
A Ddcn20_optc.c321 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total); in optc2_align_vblanks()
331 REG_GET(OTG_MASTER_UPDATE_LOCK, in optc2_align_vblanks()
337 REG_GET(OTG_V_BLANK_START_END, in optc2_align_vblanks()
339 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total); in optc2_align_vblanks()
461 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); in optc2_lock_doublebuffer_enable()
463 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start); in optc2_lock_doublebuffer_enable()
533 REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate); in optc2_get_last_used_drr_vtotal()
A Ddcn20_dsc.c157 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc2_read_state()
158 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); in dsc2_read_state()
159 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); in dsc2_read_state()
160 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); in dsc2_read_state()
161 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); in dsc2_read_state()
162 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); in dsc2_read_state()
163 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); in dsc2_read_state()
164 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); in dsc2_read_state()
238 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_enable()
263 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_disable()
A Ddcn20_dwb.c177 REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked); in dwb2_update()
204 REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled); in dwb2_is_enabled()
205 REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en); in dwb2_is_enabled()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hubp.c95 REG_GET(DCHUBP_CNTL, in hubp1_get_underflow_status()
878 REG_GET(HUBPRET_CONTROL, in hubp1_read_state_common()
907 REG_GET(BLANK_OFFSET_1, in hubp1_read_state_common()
910 REG_GET(DST_DIMENSIONS, in hubp1_read_state_common()
941 REG_GET(NOM_PARAMETERS_0, in hubp1_read_state_common()
945 REG_GET(NOM_PARAMETERS_1, in hubp1_read_state_common()
948 REG_GET(NOM_PARAMETERS_4, in hubp1_read_state_common()
951 REG_GET(NOM_PARAMETERS_5, in hubp1_read_state_common()
983 REG_GET(NOM_PARAMETERS_6, in hubp1_read_state_common()
986 REG_GET(NOM_PARAMETERS_7, in hubp1_read_state_common()
[all …]
A Ddcn10_mpc.c141 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_is_mpcc_idle()
142 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
143 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); in mpc1_is_mpcc_idle()
155 REG_GET(MPCC_TOP_SEL[mpcc_id], in mpc1_assert_mpcc_idle_before_connect()
386 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_mpc_init_single_inst()
413 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); in mpc1_init_mpcc_list_from_hw()
417 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
418 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_init_mpcc_list_from_hw()
419 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); in mpc1_init_mpcc_list_from_hw()
453 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc1_read_mpcc_state()
[all …]
A Ddcn10_optc.c748 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_enable_reset_trigger()
1309 REG_GET(OTG_STEREO_STATUS, in optc1_is_stereo_left_eye()
1346 REG_GET(OTG_CONTROL, in optc1_read_otg_state()
1353 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_read_otg_state()
1356 REG_GET(OTG_V_TOTAL, in optc1_read_otg_state()
1359 REG_GET(OTG_V_TOTAL_MAX, in optc1_read_otg_state()
1362 REG_GET(OTG_V_TOTAL_MIN, in optc1_read_otg_state()
1383 REG_GET(OTG_H_SYNC_A_CNTL, in optc1_read_otg_state()
1386 REG_GET(OTG_H_TOTAL, in optc1_read_otg_state()
1411 REG_GET(OTG_CONTROL, in optc1_get_otg_active_size()
[all …]
A Ddcn10_dpp.c99 REG_GET(DPP_CONTROL, in dpp_read_state()
101 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
103 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
105 REG_GET(CM_DGAM_CONTROL, in dpp_read_state()
107 REG_GET(CM_RGAM_CONTROL, in dpp_read_state()
109 REG_GET(CM_GAMUT_REMAP_CONTROL, in dpp_read_state()
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_panel_cntl.c57 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dcn301_get_16_bit_backlight_from_pwm()
58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dcn301_get_16_bit_backlight_from_pwm()
60 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &bl_pwm); in dcn301_get_16_bit_backlight_from_pwm()
61 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dcn301_get_16_bit_backlight_from_pwm()
106 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dcn301_panel_cntl_hw_init()
134 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_panel_cntl_hw_init()
163 REG_GET(PWRSEQ_CNTL, PANEL_BLON, &value); in dcn301_is_panel_backlight_on()
173 REG_GET(PWRSEQ_STATE, PANEL_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dcn301_is_panel_powered_on()
191 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dcn301_store_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_hubp.c88 REG_GET(VBLANK_PARAMETERS_5, in apply_DEDCN21_142_wa_for_hostvm_deadline()
96 REG_GET(VBLANK_PARAMETERS_6, in apply_DEDCN21_142_wa_for_hostvm_deadline()
104 REG_GET(FLIP_PARAMETERS_3, in apply_DEDCN21_142_wa_for_hostvm_deadline()
112 REG_GET(FLIP_PARAMETERS_4, in apply_DEDCN21_142_wa_for_hostvm_deadline()
265 REG_GET(HUBPRET_CONTROL, in hubp21_validate_dml_output()
358 REG_GET(BLANK_OFFSET_1, in hubp21_validate_dml_output()
360 REG_GET(DST_DIMENSIONS, in hubp21_validate_dml_output()
399 REG_GET(NOM_PARAMETERS_4, in hubp21_validate_dml_output()
401 REG_GET(NOM_PARAMETERS_5, in hubp21_validate_dml_output()
417 REG_GET(NOM_PARAMETERS_6, in hubp21_validate_dml_output()
[all …]
A Ddcn21_hubbub.c628 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, in hubbub21_wm_read_state()
631 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, in hubbub21_wm_read_state()
634 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, in hubbub21_wm_read_state()
642 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, in hubbub21_wm_read_state()
645 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, in hubbub21_wm_read_state()
648 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, in hubbub21_wm_read_state()
656 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, in hubbub21_wm_read_state()
659 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, in hubbub21_wm_read_state()
662 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, in hubbub21_wm_read_state()
670 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, in hubbub21_wm_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_panel_cntl.c58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dce_get_16_bit_backlight_from_pwm()
59 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dce_get_16_bit_backlight_from_pwm()
62 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in dce_get_16_bit_backlight_from_pwm()
63 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dce_get_16_bit_backlight_from_pwm()
99 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_panel_cntl_hw_init()
119 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_panel_cntl_hw_init()
153 REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state); in dce_is_panel_backlight_on()
166 REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dce_is_panel_powered_on()
184 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_store_backlight_level()
A Ddce_i2c_hw.c77 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in get_channel_status()
124 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); in process_channel_reply()
136 REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status); in is_engine_available()
140 REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate); in is_engine_available()
151 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in is_hw_busy()
366 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in release_engine()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_hpo_dp_stream_encoder.c473 REG_GET(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, in dcn31_hpo_dp_stream_enc_update_dp_info_packets()
515 REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp0_enabled); in hpo_dp_is_gsp_enabled()
516 REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp2_enabled); in hpo_dp_is_gsp_enabled()
678 REG_GET(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
680 REG_GET(DP_SYM32_ENC_VID_STREAM_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
682 REG_GET(DP_STREAM_ENC_INPUT_MUX_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
690 REG_GET(DP_SYM32_ENC_SDP_CONTROL, in dcn31_hpo_dp_stream_enc_read_state()
695 REG_GET(DP_STREAM_MAPPER_CONTROL0, in dcn31_hpo_dp_stream_enc_read_state()
699 REG_GET(DP_STREAM_MAPPER_CONTROL1, in dcn31_hpo_dp_stream_enc_read_state()
703 REG_GET(DP_STREAM_MAPPER_CONTROL2, in dcn31_hpo_dp_stream_enc_read_state()
[all …]
A Ddcn31_dio_link_encoder.c545 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); in dcn31_link_encoder_is_in_alt_mode()
554 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); in dcn31_link_encoder_is_in_alt_mode()
557 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); in dcn31_link_encoder_is_in_alt_mode()
579 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); in dcn31_link_encoder_get_max_link_cap()
584 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); in dcn31_link_encoder_get_max_link_cap()
586 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); in dcn31_link_encoder_get_max_link_cap()
A Ddcn31_hpo_dp_link_encoder.c58 REG_GET(DP_DPHY_SYM32_STATUS, in dcn31_hpo_dp_link_enc_enable()
440 REG_GET(RDPCSTX_PHY_CNTL6[enc->transmitter], RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); in dcn31_hpo_dp_link_enc_is_in_alt_mode()
452 REG_GET(DP_DPHY_SYM32_STATUS, in dcn31_hpo_dp_link_enc_read_state()
454 REG_GET(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_read_state()
456 REG_GET(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_read_state()
/linux/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn20.c72 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn20_get_fb_base_offset()
75 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn20_get_fb_base_offset()
100 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn20_reset()
347 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); in dmub_dcn20_is_hw_init()
356 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn20_is_supported()
452 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn20_get_diagnostic_data()
455 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn20_get_diagnostic_data()
458 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn20_get_diagnostic_data()
461 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn20_get_diagnostic_data()
464 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); in dmub_dcn20_get_diagnostic_data()
[all …]
A Ddmub_dcn31.c68 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn31_get_fb_base_offset()
71 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn31_get_fb_base_offset()
89 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn31_reset()
277 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); in dmub_dcn31_is_hw_init()
286 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn31_is_supported()
422 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn31_get_diagnostic_data()
425 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn31_get_diagnostic_data()
428 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn31_get_diagnostic_data()
431 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn31_get_diagnostic_data()
434 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); in dmub_dcn31_get_diagnostic_data()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/
A Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
46 REG_GET(A_reg, A, &gpio->store.a); in store_registers()
47 REG_GET(EN_reg, EN, &gpio->store.en); in store_registers()
86 REG_GET(Y_reg, Y, value); in dal_hw_gpio_get_value()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dio_stream_encoder.c410 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc3_read_state()
412 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc3_read_state()
413 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); in enc3_read_state()
415 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc3_read_state()
416 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc3_read_state()
418 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); in enc3_read_state()
419 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc3_read_state()
475 REG_GET(DP_SEC_METADATA_TRANSMISSION, in enc3_stream_encoder_update_dp_info_packets()
A Ddcn30_dwb.c144 REG_GET(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, &pre_locked); in dwb3_update()
177 REG_GET(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, &dwb_enabled); in dwb3_is_enabled()
178 REG_GET(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, &fc_frame_capture_en); in dwb3_is_enabled()
A Ddcn30_dpp.c49 REG_GET(DPP_CONTROL, in dpp30_read_state()
93 REG_GET(CM_POST_CSC_CONTROL, in dpp3_program_post_csc()
503 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state); in dpp3_deferred_update()
521 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state); in dpp3_deferred_update()
530 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state); in dpp3_deferred_update()
730 REG_GET(CM_BLNDGAM_CONTROL, in dpp3_get_blndgam_current()
732 REG_GET(CM_BLNDGAM_CONTROL, in dpp3_get_blndgam_current()
831 REG_GET(CM_SHAPER_CONTROL, in dpp3_get_shaper_current()
1218 REG_GET(CM_3DLUT_READ_WRITE_CONTROL, in get3dlut_config()
1220 REG_GET(CM_3DLUT_MODE, in get3dlut_config()
[all …]
A Ddcn30_mpc.c54 REG_GET(DWB_MUX[dwb_id], MPC_DWB0_MUX_STATUS, &status); in mpc3_is_dwb_idle()
442 REG_GET(SHAPER_CONTROL[rmu_idx], in mpc3_get_shaper_current()
829 REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, &power_status_shaper); in mpc3_power_on_shaper_3dlut()
830 REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, &power_status_3dlut); in mpc3_power_on_shaper_3dlut()
839 REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, &power_status_shaper); in mpc3_power_on_shaper_3dlut()
840 REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, &power_status_3dlut); in mpc3_power_on_shaper_3dlut()
925 REG_GET(RMU_3DLUT_MODE[rmu_idx], in get3dlut_config()
928 REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[rmu_idx], in get3dlut_config()
950 REG_GET(RMU_3DLUT_MODE[rmu_idx], MPC_RMU_3DLUT_SIZE, &lut_size); in get3dlut_config()
1339 REG_GET(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, &status); in mpc3_get_rmu_mux_status()
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