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Searched refs:REG_WRITE (Results 1 – 25 of 98) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn30.c102 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
111 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
143 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0); in dmub_dcn30_setup_windows()
144 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0); in dmub_dcn30_setup_windows()
145 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0); in dmub_dcn30_setup_windows()
146 REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0); in dmub_dcn30_setup_windows()
151 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
169 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
179 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
186 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
[all …]
A Ddmub_dcn20.c139 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn20_reset()
140 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn20_reset()
141 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn20_reset()
142 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn20_reset()
143 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn20_reset()
212 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0); in dmub_dcn20_setup_windows()
213 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0); in dmub_dcn20_setup_windows()
292 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn20_set_inbox1_wptr()
322 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn20_set_outbox1_rptr()
340 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); in dmub_dcn20_set_outbox0_rptr()
[all …]
A Ddmub_dcn31.c124 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn31_reset()
125 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn31_reset()
126 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn31_reset()
127 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn31_reset()
128 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn31_reset()
243 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn31_set_inbox1_wptr()
268 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); in dmub_dcn31_set_outbox1_rptr()
294 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); in dmub_dcn31_set_gpint()
319 REG_WRITE(DMCUB_GPINT_DATAOUT, 0); in dmub_dcn31_get_gpint_dataout()
347 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); in dmub_dcn31_enable_dmub_boot_options()
[all …]
/linux/drivers/net/wireless/ath/
A Dkey.c57 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ath_hw_keyreset()
58 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ath_hw_keyreset()
59 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ath_hw_keyreset()
60 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ath_hw_keyreset()
61 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ath_hw_keyreset()
63 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ath_hw_keyreset()
64 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ath_hw_keyreset()
69 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); in ath_hw_keyreset()
75 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), in ath_hw_keyreset()
255 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), in ath_hw_set_keycache_entry()
[all …]
A Dhw.c24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
123 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); in ath_hw_setbssidmask()
126 REG_WRITE(ah, AR_STA_ID1, id1); in ath_hw_setbssidmask()
128 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask)); in ath_hw_setbssidmask()
129 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4)); in ath_hw_setbssidmask()
148 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath_hw_cycle_counters_update()
157 REG_WRITE(ah, AR_CCCNT, 0); in ath_hw_cycle_counters_update()
158 REG_WRITE(ah, AR_RFCNT, 0); in ath_hw_cycle_counters_update()
159 REG_WRITE(ah, AR_RCCNT, 0); in ath_hw_cycle_counters_update()
160 REG_WRITE(ah, AR_TFCNT, 0); in ath_hw_cycle_counters_update()
[all …]
/linux/drivers/gpu/drm/gma500/
A Doaktrail_hdmi.c296 REG_WRITE(DPLL_STATUS, 0x1); in oaktrail_crtc_hdmi_mode_set()
327 REG_WRITE(htot_reg, temp); in oaktrail_crtc_hdmi_mode_set()
347 REG_WRITE(dsppos_reg, 0); in oaktrail_crtc_hdmi_mode_set()
372 REG_WRITE(dspcntr_reg, dspcntr); in oaktrail_crtc_hdmi_mode_set()
422 REG_WRITE(DPLL_STATUS, 0x1); in oaktrail_crtc_hdmi_dpms()
472 REG_WRITE(DSPARB, 0x00003fbf); in oaktrail_crtc_hdmi_dpms()
475 REG_WRITE(0x70034, 0x3f880a0a); in oaktrail_crtc_hdmi_dpms()
478 REG_WRITE(0x70038, 0x0b060808); in oaktrail_crtc_hdmi_dpms()
481 REG_WRITE(0x70050, 0x08030404); in oaktrail_crtc_hdmi_dpms()
484 REG_WRITE(0x70054, 0x04040404); in oaktrail_crtc_hdmi_dpms()
[all …]
A Dgma_display.c107 REG_WRITE(map->cntr, dspcntr); in gma_pipe_set_base()
121 REG_WRITE(map->surf, start); in gma_pipe_set_base()
156 REG_WRITE(palreg + 4 * i, in gma_crtc_load_lut()
234 REG_WRITE(map->cntr, in gma_crtc_dpms()
283 REG_WRITE(map->cntr, in gma_crtc_dpms()
318 REG_WRITE(DSPARB, 0x3F3E); in gma_crtc_dpms()
344 REG_WRITE(control, temp); in gma_crtc_cursor_set()
345 REG_WRITE(base, 0); in gma_crtc_cursor_set()
421 REG_WRITE(control, temp); in gma_crtc_cursor_set()
422 REG_WRITE(base, addr); in gma_crtc_cursor_set()
[all …]
A Dcdv_intel_display.c139 REG_WRITE(SB_ADDR, reg); in cdv_sb_read()
140 REG_WRITE(SB_PCKT, in cdv_sb_read()
174 REG_WRITE(SB_ADDR, reg); in cdv_sb_write()
175 REG_WRITE(SB_DATA, val); in cdv_sb_write()
176 REG_WRITE(SB_PCKT, in cdv_sb_write()
201 REG_WRITE(DPIO_CFG, 0); in cdv_sb_reset()
504 REG_WRITE(DSPFW1, fw); in cdv_update_wm()
511 REG_WRITE(DSPFW2, fw); in cdv_update_wm()
761 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
792 REG_WRITE(map->size, in cdv_intel_crtc_mode_set()
[all …]
A Dcdv_device.c35 REG_WRITE(vga_reg, VGA_DISP_DISABLE); in cdv_disable_vga()
137 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | in cdv_set_brightness()
329 REG_WRITE(DPIO_CFG, 0); in cdv_restore_display_registers()
346 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); in cdv_restore_display_registers()
347 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); in cdv_restore_display_registers()
348 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); in cdv_restore_display_registers()
353 REG_WRITE(DSPARB, regs->cdv.saveDSPARB); in cdv_restore_display_registers()
354 REG_WRITE(ADPA, regs->cdv.saveADPA); in cdv_restore_display_registers()
357 REG_WRITE(LVDS, regs->cdv.saveLVDS); in cdv_restore_display_registers()
455 REG_WRITE(PORT_HOTPLUG_EN, hotplug); in cdv_hotplug_enable()
[all …]
A Dpsb_intel_display.c208 REG_WRITE(PFIT_CONTROL, 0); in psb_intel_crtc_mode_set()
213 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
244 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
248 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
249 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
255 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
276 REG_WRITE(map->size, in psb_intel_crtc_mode_set()
278 REG_WRITE(map->pos, 0); in psb_intel_crtc_mode_set()
279 REG_WRITE(map->src, in psb_intel_crtc_mode_set()
281 REG_WRITE(map->conf, pipeconf); in psb_intel_crtc_mode_set()
[all …]
A Dpsb_intel_lvds.c146 REG_WRITE(BLC_PWM_CTL, in psb_lvds_pwm_set_brightness()
190 REG_WRITE(BLC_PWM_CTL, in psb_intel_lvds_set_backlight()
219 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
230 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
310 REG_WRITE(LVDSPP_ON, lvds_priv->savePP_ON); in psb_intel_lvds_restore()
311 REG_WRITE(LVDSPP_OFF, lvds_priv->savePP_OFF); in psb_intel_lvds_restore()
313 REG_WRITE(PP_CYCLE, lvds_priv->savePP_CYCLE); in psb_intel_lvds_restore()
315 REG_WRITE(LVDS, lvds_priv->saveLVDS); in psb_intel_lvds_restore()
318 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_restore()
324 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_restore()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
A Dar9003_wow.c44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
62 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_set_powermode_wow_sleep()
235 REG_WRITE(ah, AR_WOW_PATTERN, in ath9k_hw_wow_wakeup()
237 REG_WRITE(ah, AR_MAC_PCU_WOW4, in ath9k_hw_wow_wakeup()
243 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_wow_wakeup()
286 REG_WRITE(ah, AR_WA, wa_reg); in ath9k_hw_wow_set_arwr_reg()
376 REG_WRITE(ah, AR_WOW_KEEP_ALIVE, keep_alive); in ath9k_hw_wow_enable()
405 REG_WRITE(ah, AR_WOW_PATTERN, magic_pattern); in ath9k_hw_wow_enable()
411 REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B, in ath9k_hw_wow_enable()
433 REG_WRITE(ah, AR_PCIE_PM_CTRL, host_pm_ctrl); in ath9k_hw_wow_enable()
[all …]
A Dar9003_aic.c180 REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B0, in ar9003_aic_cal_start()
190 REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1, in ar9003_aic_cal_start()
197 REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B0, in ar9003_aic_cal_start()
206 REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B1, in ar9003_aic_cal_start()
558 REG_WRITE(ah, 0xa6b0, 0x80); in ar9003_aic_start_normal()
559 REG_WRITE(ah, 0xa6b4, 0x5b2df0); in ar9003_aic_start_normal()
561 REG_WRITE(ah, 0xa6bc, 0x1219a4b); in ar9003_aic_start_normal()
562 REG_WRITE(ah, 0xa6c0, 0x1e01); in ar9003_aic_start_normal()
563 REG_WRITE(ah, 0xb6b4, 0xf0); in ar9003_aic_start_normal()
564 REG_WRITE(ah, 0xb6c0, 0x1e01); in ar9003_aic_start_normal()
[all …]
A Dar5008_phy.c236 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
239 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
268 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
475 REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ar5008_hw_spur_mitigate()
486 REG_WRITE(ah, AR_PHY_TIMING11, new); in ar5008_hw_spur_mitigate()
631 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
709 REG_WRITE(ah, AR_PHY_TURBO, phymode); in ar5008_hw_set_channel_regs()
760 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
792 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
845 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar5008_hw_set_rfmode()
[all …]
A Dhw.c721 REG_WRITE(ah, AR_QOS_NO_ACK, in ath9k_hw_init_qos()
1435 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1465 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset_power_on()
1635 REG_WRITE(ah, AR_NAV, 0); in ath9k_hw_check_nav()
1721 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset_opmode()
1933 REG_WRITE(ah, in ath9k_hw_reset()
1947 REG_WRITE(ah, in ath9k_hw_reset()
2020 REG_WRITE(ah, AR_OBS, 8); in ath9k_hw_reset()
2363 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
2372 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
[all …]
A Dar9003_mci.c48 REG_WRITE(ah, address, bit_position); in ar9003_mci_wait_for_interrupt()
58 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_wait_for_interrupt()
234 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); in ar9003_mci_prep_interface()
237 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_prep_interface()
314 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_prep_interface()
469 REG_WRITE(ah, AR_OBS, 0x4b); in ar9003_mci_observation_set_up()
1048 REG_WRITE(ah, AR_BTCOEX_CTRL, 0); in ar9003_mci_stop_bt()
1199 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_send_message()
1209 REG_WRITE(ah, AR_MCI_COMMAND0, in ar9003_mci_send_message()
1285 REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00); in ar9003_mci_cleanup()
[all …]
A Dar9002_phy.c101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
240 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); in ar9002_hw_spur_mitigate()
270 REG_WRITE(ah, AR_PHY_TIMING11, newVal); in ar9002_hw_spur_mitigate()
451 REG_WRITE(ah, AR_PHY_SWITCH_COM, 0); in ar9002_hw_set_bt_ant_diversity()
560 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9002_hw_tx99_start()
561 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); in ar9002_hw_tx99_start()
562 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); in ar9002_hw_tx99_start()
563 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); in ar9002_hw_tx99_start()
564 REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum); in ar9002_hw_tx99_start()
[all …]
A Dar9002_hw.c223 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ar9002_hw_configpcipowersave()
224 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ar9002_hw_configpcipowersave()
227 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); in ar9002_hw_configpcipowersave()
228 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); in ar9002_hw_configpcipowersave()
289 REG_WRITE(ah, AR_WA, val); in ar9002_hw_configpcipowersave()
317 REG_WRITE(ah, AR_WA, val); in ar9002_hw_configpcipowersave()
331 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); in ar9002_hw_get_radiorev()
333 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); in ar9002_hw_get_radiorev()
347 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar9002_hw_rf_claim()
448 REG_WRITE(ah, reg, val|val_orig); in ar9002_hw_load_ani_reg()
[all …]
A Dmac.c32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
61 REG_WRITE(ah, AR_Q_TXE, 1 << q); in ath9k_hw_txstart()
123 REG_WRITE(ah, AR_TXCFG, in ath9k_hw_updatetxtriglevel()
166 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_abort_tx_dma()
187 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_stop_dma_queue()
390 REG_WRITE(ah, AR_DLCL_IFS(q), in ath9k_hw_resettxqueue()
403 REG_WRITE(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
406 REG_WRITE(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
410 REG_WRITE(ah, AR_QCBRCFG(q), in ath9k_hw_resettxqueue()
[all …]
A Dbtcoex.c333 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode); in ath9k_hw_btcoex_enable_3wire()
334 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ath9k_hw_btcoex_enable_3wire()
343 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), in ath9k_hw_btcoex_enable_3wire()
351 REG_WRITE(ah, 0x50040, val); in ath9k_hw_btcoex_enable_3wire()
368 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), in ath9k_hw_btcoex_enable_mci()
383 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), in ath9k_hw_btcoex_disable_mci()
436 REG_WRITE(ah, AR_BT_COEX_MODE2, 0); in ath9k_hw_btcoex_disable()
439 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); in ath9k_hw_btcoex_disable()
440 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); in ath9k_hw_btcoex_disable()
442 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 0); in ath9k_hw_btcoex_disable()
[all …]
A Dani.c135 REG_WRITE(ah, AR_PHY_ERR_1, 0); in ath9k_ani_restart()
136 REG_WRITE(ah, AR_PHY_ERR_2, 0); in ath9k_ani_restart()
137 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_restart()
138 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_restart()
451 REG_WRITE(ah, AR_FILT_OFDM, 0); in ath9k_enable_mib_counters()
452 REG_WRITE(ah, AR_FILT_CCK, 0); in ath9k_enable_mib_counters()
453 REG_WRITE(ah, AR_MIBC, in ath9k_enable_mib_counters()
469 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath9k_hw_disable_mib_counters()
471 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); in ath9k_hw_disable_mib_counters()
472 REG_WRITE(ah, AR_FILT_OFDM, 0); in ath9k_hw_disable_mib_counters()
[all …]
A Dar9003_phy.c688 REG_WRITE(ah, AR_SELFGEN_MASK, tx); in ar9003_hw_set_chain_masks()
772 REG_WRITE(ah, reg, val); in ar9003_hw_prog_ini()
999 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar9003_hw_set_rfmode()
1071 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar9003_hw_rfbus_done()
1809 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9003_hw_tx99_start()
1810 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); in ar9003_hw_tx99_start()
2019 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
2024 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
2072 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
2097 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
[all …]
A Dar9003_rtt.c40 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); in ar9003_hw_rtt_enable()
45 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); in ar9003_hw_rtt_disable()
78 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
83 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
87 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
96 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
150 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
154 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_hubbub.c404 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg); in hubbub3_init_watermarks()
405 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg); in hubbub3_init_watermarks()
406 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg); in hubbub3_init_watermarks()
409 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg); in hubbub3_init_watermarks()
410 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg); in hubbub3_init_watermarks()
411 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg); in hubbub3_init_watermarks()
414 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg); in hubbub3_init_watermarks()
415 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg); in hubbub3_init_watermarks()
416 REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg); in hubbub3_init_watermarks()
429 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg); in hubbub3_init_watermarks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_abm.c70 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); in dce_abm_set_pipe()
115 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); in dmcu_set_backlight_level()
131 REG_WRITE(BIOS_SCRATCH_2, s2); in dmcu_set_backlight_level()
142 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); in dce_abm_init()
143 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); in dce_abm_init()
144 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); in dce_abm_init()
145 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); in dce_abm_init()
146 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101); in dce_abm_init()

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