Searched refs:RVU_PF_VFFLR_INTX (Results 1 – 5 of 5) sorted by relevance
/linux/drivers/crypto/marvell/octeontx2/ |
A D | otx2_cptpf_main.c | 70 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFFLR_INTX(0), in cptpf_enable_vf_flr_me_intrs() 86 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFFLR_INTX(1), in cptpf_enable_vf_flr_me_intrs() 176 RVU_PF_VFFLR_INTX(reg)); in cptpf_vf_flr_intr() 187 RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); in cptpf_vf_flr_intr()
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/linux/drivers/net/ethernet/marvell/octeontx2/nic/ |
A D | otx2_reg.h | 26 #define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3) macro
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A D | otx2_pf.c | 152 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); in otx2_pf_flr_intr_handler() 162 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); in otx2_pf_flr_intr_handler() 252 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); in otx2_register_flr_me_intr() 262 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); in otx2_register_flr_me_intr()
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/linux/drivers/net/ethernet/marvell/octeontx2/af/ |
A D | rvu_reg.h | 92 #define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3) macro
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A D | rvu.c | 2622 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); in rvu_afvf_queue_flr_work() 2630 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); in rvu_afvf_queue_flr_work() 3030 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); in rvu_enable_afvf_intr() 3042 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
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