1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Internal header file for Samsung S3C2410 serial ports (UART0-2) 4 * 5 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 6 * 7 * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk) 8 * 9 * Adapted from: 10 * 11 * Internal header file for MX1ADS serial ports (UART1 & 2) 12 * 13 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 14 */ 15 16 #ifndef __ASM_ARM_REGS_SERIAL_H 17 #define __ASM_ARM_REGS_SERIAL_H 18 19 #define S3C2410_URXH (0x24) 20 #define S3C2410_UTXH (0x20) 21 #define S3C2410_ULCON (0x00) 22 #define S3C2410_UCON (0x04) 23 #define S3C2410_UFCON (0x08) 24 #define S3C2410_UMCON (0x0C) 25 #define S3C2410_UBRDIV (0x28) 26 #define S3C2410_UTRSTAT (0x10) 27 #define S3C2410_UERSTAT (0x14) 28 #define S3C2410_UFSTAT (0x18) 29 #define S3C2410_UMSTAT (0x1C) 30 #define USI_CON (0xC4) 31 #define USI_OPTION (0xC8) 32 33 #define USI_CON_RESET (1<<0) 34 #define USI_CON_RESET_MASK (1<<0) 35 36 #define USI_OPTION_HWACG_CLKREQ_ON (1<<1) 37 #define USI_OPTION_HWACG_CLKSTOP_ON (1<<2) 38 #define USI_OPTION_HWACG_MASK (3<<1) 39 40 #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) 41 42 #define S3C2410_LCON_CS5 (0x0) 43 #define S3C2410_LCON_CS6 (0x1) 44 #define S3C2410_LCON_CS7 (0x2) 45 #define S3C2410_LCON_CS8 (0x3) 46 #define S3C2410_LCON_CSMASK (0x3) 47 48 #define S3C2410_LCON_PNONE (0x0) 49 #define S3C2410_LCON_PEVEN (0x5 << 3) 50 #define S3C2410_LCON_PODD (0x4 << 3) 51 #define S3C2410_LCON_PMASK (0x7 << 3) 52 53 #define S3C2410_LCON_STOPB (1<<2) 54 #define S3C2410_LCON_IRM (1<<6) 55 56 #define S3C2440_UCON_CLKMASK (3<<10) 57 #define S3C2440_UCON_CLKSHIFT (10) 58 #define S3C2440_UCON_PCLK (0<<10) 59 #define S3C2440_UCON_UCLK (1<<10) 60 #define S3C2440_UCON_PCLK2 (2<<10) 61 #define S3C2440_UCON_FCLK (3<<10) 62 #define S3C2443_UCON_EPLL (3<<10) 63 64 #define S3C6400_UCON_CLKMASK (3<<10) 65 #define S3C6400_UCON_CLKSHIFT (10) 66 #define S3C6400_UCON_PCLK (0<<10) 67 #define S3C6400_UCON_PCLK2 (2<<10) 68 #define S3C6400_UCON_UCLK0 (1<<10) 69 #define S3C6400_UCON_UCLK1 (3<<10) 70 71 #define S3C2440_UCON2_FCLK_EN (1<<15) 72 #define S3C2440_UCON0_DIVMASK (15 << 12) 73 #define S3C2440_UCON1_DIVMASK (15 << 12) 74 #define S3C2440_UCON2_DIVMASK (7 << 12) 75 #define S3C2440_UCON_DIVSHIFT (12) 76 77 #define S3C2412_UCON_CLKMASK (3<<10) 78 #define S3C2412_UCON_CLKSHIFT (10) 79 #define S3C2412_UCON_UCLK (1<<10) 80 #define S3C2412_UCON_USYSCLK (3<<10) 81 #define S3C2412_UCON_PCLK (0<<10) 82 #define S3C2412_UCON_PCLK2 (2<<10) 83 84 #define S3C2410_UCON_CLKMASK (1 << 10) 85 #define S3C2410_UCON_CLKSHIFT (10) 86 #define S3C2410_UCON_UCLK (1<<10) 87 #define S3C2410_UCON_SBREAK (1<<4) 88 89 #define S3C2410_UCON_TXILEVEL (1<<9) 90 #define S3C2410_UCON_RXILEVEL (1<<8) 91 #define S3C2410_UCON_TXIRQMODE (1<<2) 92 #define S3C2410_UCON_RXIRQMODE (1<<0) 93 #define S3C2410_UCON_RXFIFO_TOI (1<<7) 94 #define S3C2443_UCON_RXERR_IRQEN (1<<6) 95 #define S3C2443_UCON_LOOPBACK (1<<5) 96 97 #define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 98 S3C2410_UCON_RXILEVEL | \ 99 S3C2410_UCON_TXIRQMODE | \ 100 S3C2410_UCON_RXIRQMODE | \ 101 S3C2410_UCON_RXFIFO_TOI) 102 103 #define S3C64XX_UCON_TXBURST_1 (0<<20) 104 #define S3C64XX_UCON_TXBURST_4 (1<<20) 105 #define S3C64XX_UCON_TXBURST_8 (2<<20) 106 #define S3C64XX_UCON_TXBURST_16 (3<<20) 107 #define S3C64XX_UCON_TXBURST_MASK (0xf<<20) 108 #define S3C64XX_UCON_RXBURST_1 (0<<16) 109 #define S3C64XX_UCON_RXBURST_4 (1<<16) 110 #define S3C64XX_UCON_RXBURST_8 (2<<16) 111 #define S3C64XX_UCON_RXBURST_16 (3<<16) 112 #define S3C64XX_UCON_RXBURST_MASK (0xf<<16) 113 #define S3C64XX_UCON_TIMEOUT_SHIFT (12) 114 #define S3C64XX_UCON_TIMEOUT_MASK (0xf<<12) 115 #define S3C64XX_UCON_EMPTYINT_EN (1<<11) 116 #define S3C64XX_UCON_DMASUS_EN (1<<10) 117 #define S3C64XX_UCON_TXINT_LEVEL (1<<9) 118 #define S3C64XX_UCON_RXINT_LEVEL (1<<8) 119 #define S3C64XX_UCON_TIMEOUT_EN (1<<7) 120 #define S3C64XX_UCON_ERRINT_EN (1<<6) 121 #define S3C64XX_UCON_TXMODE_DMA (2<<2) 122 #define S3C64XX_UCON_TXMODE_CPU (1<<2) 123 #define S3C64XX_UCON_TXMODE_MASK (3<<2) 124 #define S3C64XX_UCON_RXMODE_DMA (2<<0) 125 #define S3C64XX_UCON_RXMODE_CPU (1<<0) 126 #define S3C64XX_UCON_RXMODE_MASK (3<<0) 127 128 #define S3C2410_UFCON_FIFOMODE (1<<0) 129 #define S3C2410_UFCON_TXTRIG0 (0<<6) 130 #define S3C2410_UFCON_RXTRIG8 (1<<4) 131 #define S3C2410_UFCON_RXTRIG12 (2<<4) 132 133 /* S3C2440 FIFO trigger levels */ 134 #define S3C2440_UFCON_RXTRIG1 (0<<4) 135 #define S3C2440_UFCON_RXTRIG8 (1<<4) 136 #define S3C2440_UFCON_RXTRIG16 (2<<4) 137 #define S3C2440_UFCON_RXTRIG32 (3<<4) 138 139 #define S3C2440_UFCON_TXTRIG0 (0<<6) 140 #define S3C2440_UFCON_TXTRIG16 (1<<6) 141 #define S3C2440_UFCON_TXTRIG32 (2<<6) 142 #define S3C2440_UFCON_TXTRIG48 (3<<6) 143 144 #define S3C2410_UFCON_RESETBOTH (3<<1) 145 #define S3C2410_UFCON_RESETTX (1<<2) 146 #define S3C2410_UFCON_RESETRX (1<<1) 147 148 #define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 149 S3C2410_UFCON_TXTRIG0 | \ 150 S3C2410_UFCON_RXTRIG8 ) 151 152 #define S3C2410_UMCOM_AFC (1<<4) 153 #define S3C2410_UMCOM_RTS_LOW (1<<0) 154 155 #define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */ 156 #define S3C2412_UMCON_AFC_56 (1<<5) 157 #define S3C2412_UMCON_AFC_48 (2<<5) 158 #define S3C2412_UMCON_AFC_40 (3<<5) 159 #define S3C2412_UMCON_AFC_32 (4<<5) 160 #define S3C2412_UMCON_AFC_24 (5<<5) 161 #define S3C2412_UMCON_AFC_16 (6<<5) 162 #define S3C2412_UMCON_AFC_8 (7<<5) 163 164 #define S3C2410_UFSTAT_TXFULL (1<<9) 165 #define S3C2410_UFSTAT_RXFULL (1<<8) 166 #define S3C2410_UFSTAT_TXMASK (15<<4) 167 #define S3C2410_UFSTAT_TXSHIFT (4) 168 #define S3C2410_UFSTAT_RXMASK (15<<0) 169 #define S3C2410_UFSTAT_RXSHIFT (0) 170 171 /* UFSTAT S3C2443 same as S3C2440 */ 172 #define S3C2440_UFSTAT_TXFULL (1<<14) 173 #define S3C2440_UFSTAT_RXFULL (1<<6) 174 #define S3C2440_UFSTAT_TXSHIFT (8) 175 #define S3C2440_UFSTAT_RXSHIFT (0) 176 #define S3C2440_UFSTAT_TXMASK (63<<8) 177 #define S3C2440_UFSTAT_RXMASK (63) 178 179 #define S3C2410_UTRSTAT_TIMEOUT (1<<3) 180 #define S3C2410_UTRSTAT_TXE (1<<2) 181 #define S3C2410_UTRSTAT_TXFE (1<<1) 182 #define S3C2410_UTRSTAT_RXDR (1<<0) 183 184 #define S3C2410_UERSTAT_OVERRUN (1<<0) 185 #define S3C2410_UERSTAT_FRAME (1<<2) 186 #define S3C2410_UERSTAT_BREAK (1<<3) 187 #define S3C2443_UERSTAT_PARITY (1<<1) 188 189 #define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \ 190 S3C2410_UERSTAT_FRAME | \ 191 S3C2410_UERSTAT_BREAK) 192 193 #define S3C2410_UMSTAT_CTS (1<<0) 194 #define S3C2410_UMSTAT_DeltaCTS (1<<2) 195 196 #define S3C2443_DIVSLOT (0x2C) 197 198 /* S3C64XX interrupt registers. */ 199 #define S3C64XX_UINTP 0x30 200 #define S3C64XX_UINTSP 0x34 201 #define S3C64XX_UINTM 0x38 202 203 #define S3C64XX_UINTM_RXD (0) 204 #define S3C64XX_UINTM_ERROR (1) 205 #define S3C64XX_UINTM_TXD (2) 206 #define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD) 207 #define S3C64XX_UINTM_ERR_MSK (1 << S3C64XX_UINTM_ERROR) 208 #define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD) 209 210 /* Following are specific to S5PV210 */ 211 #define S5PV210_UCON_CLKMASK (1<<10) 212 #define S5PV210_UCON_CLKSHIFT (10) 213 #define S5PV210_UCON_PCLK (0<<10) 214 #define S5PV210_UCON_UCLK (1<<10) 215 216 #define S5PV210_UFCON_TXTRIG0 (0<<8) 217 #define S5PV210_UFCON_TXTRIG4 (1<<8) 218 #define S5PV210_UFCON_TXTRIG8 (2<<8) 219 #define S5PV210_UFCON_TXTRIG16 (3<<8) 220 #define S5PV210_UFCON_TXTRIG32 (4<<8) 221 #define S5PV210_UFCON_TXTRIG64 (5<<8) 222 #define S5PV210_UFCON_TXTRIG128 (6<<8) 223 #define S5PV210_UFCON_TXTRIG256 (7<<8) 224 225 #define S5PV210_UFCON_RXTRIG1 (0<<4) 226 #define S5PV210_UFCON_RXTRIG4 (1<<4) 227 #define S5PV210_UFCON_RXTRIG8 (2<<4) 228 #define S5PV210_UFCON_RXTRIG16 (3<<4) 229 #define S5PV210_UFCON_RXTRIG32 (4<<4) 230 #define S5PV210_UFCON_RXTRIG64 (5<<4) 231 #define S5PV210_UFCON_RXTRIG128 (6<<4) 232 #define S5PV210_UFCON_RXTRIG256 (7<<4) 233 234 #define S5PV210_UFSTAT_TXFULL (1<<24) 235 #define S5PV210_UFSTAT_RXFULL (1<<8) 236 #define S5PV210_UFSTAT_TXMASK (255<<16) 237 #define S5PV210_UFSTAT_TXSHIFT (16) 238 #define S5PV210_UFSTAT_RXMASK (255<<0) 239 #define S5PV210_UFSTAT_RXSHIFT (0) 240 241 #define S3C2410_UCON_CLKSEL0 (1 << 0) 242 #define S3C2410_UCON_CLKSEL1 (1 << 1) 243 #define S3C2410_UCON_CLKSEL2 (1 << 2) 244 #define S3C2410_UCON_CLKSEL3 (1 << 3) 245 246 /* Default values for s5pv210 UCON and UFCON uart registers */ 247 #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 248 S3C2410_UCON_RXILEVEL | \ 249 S3C2410_UCON_TXIRQMODE | \ 250 S3C2410_UCON_RXIRQMODE | \ 251 S3C2410_UCON_RXFIFO_TOI | \ 252 S3C2443_UCON_RXERR_IRQEN) 253 254 #define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 255 S5PV210_UFCON_TXTRIG4 | \ 256 S5PV210_UFCON_RXTRIG4) 257 258 #define APPLE_S5L_UCON_RXTO_ENA 9 259 #define APPLE_S5L_UCON_RXTHRESH_ENA 12 260 #define APPLE_S5L_UCON_TXTHRESH_ENA 13 261 #define APPLE_S5L_UCON_RXTO_ENA_MSK (1 << APPLE_S5L_UCON_RXTO_ENA) 262 #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_RXTHRESH_ENA) 263 #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_TXTHRESH_ENA) 264 265 #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \ 266 S3C2410_UCON_RXIRQMODE | \ 267 S3C2410_UCON_RXFIFO_TOI) 268 269 #define APPLE_S5L_UTRSTAT_RXTHRESH (1<<4) 270 #define APPLE_S5L_UTRSTAT_TXTHRESH (1<<5) 271 #define APPLE_S5L_UTRSTAT_RXTO (1<<9) 272 #define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) 273 274 #ifndef __ASSEMBLY__ 275 276 #include <linux/serial_core.h> 277 278 /* configuration structure for per-machine configurations for the 279 * serial port 280 * 281 * the pointer is setup by the machine specific initialisation from the 282 * arch/arm/mach-s3c/ directory. 283 */ 284 285 struct s3c2410_uartcfg { 286 unsigned char hwport; /* hardware port number */ 287 unsigned char unused; 288 unsigned short flags; 289 upf_t uart_flags; /* default uart flags */ 290 unsigned int clk_sel; 291 292 unsigned int has_fracval; 293 294 unsigned long ucon; /* value of ucon for port */ 295 unsigned long ulcon; /* value of ulcon for port */ 296 unsigned long ufcon; /* value of ufcon for port */ 297 }; 298 299 #endif /* __ASSEMBLY__ */ 300 301 #endif /* __ASM_ARM_REGS_SERIAL_H */ 302 303