Home
last modified time | relevance | path

Searched refs:SCLK_UART3 (Results 1 – 25 of 27) sorted by relevance

12

/linux/include/dt-bindings/clock/
A Dexynos7-clk.h98 #define SCLK_UART3 6 macro
A Ds5pv210.h194 #define SCLK_UART3 172 macro
A Drk3188-cru-common.h23 #define SCLK_UART3 67 macro
A Dpx30-cru.h28 #define SCLK_UART3 26 macro
A Drk3288-cru.h35 #define SCLK_UART3 80 macro
A Drk3308-cru.h24 #define SCLK_UART3 20 macro
A Drk3368-cru.h33 #define SCLK_UART3 80 macro
A Drk3399-cru.h41 #define SCLK_UART3 84 macro
A Drk3568-cru.h358 #define SCLK_UART3 295 macro
/linux/drivers/clk/samsung/
A Dclk-s5pv210.c675 GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,
A Dclk-exynos7.c782 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
/linux/arch/arm/boot/dts/
A Drk3xxx.dtsi430 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
A Ds5pv210.dtsi360 <&clocks SCLK_UART3>;
A Drk3288.dtsi422 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
/linux/drivers/clk/rockchip/
A Dclk-rk3188.c272 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT,
A Dclk-rk3368.c267 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
A Dclk-rk3288.c275 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
A Dclk-px30.c697 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
A Dclk-rk3308.c367 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
A Dclk-rk3399.c274 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
A Dclk-rk3568.c1226 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
/linux/arch/arm64/boot/dts/exynos/
A Dexynos7.dtsi298 <&clock_peric1 SCLK_UART3>;
/linux/arch/arm64/boot/dts/rockchip/
A Drk356x.dtsi777 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
A Drk3368.dtsi352 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
A Drk3308.dtsi333 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;

Completed in 57 milliseconds

12