1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Synopsys DesignWare Multimedia Card Interface driver
4  *  (Based on NXP driver for lpc 31xx)
5  *
6  * Copyright (C) 2009 NXP Semiconductors
7  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8  */
9 
10 #ifndef _DW_MMC_H_
11 #define _DW_MMC_H_
12 
13 #include <linux/scatterlist.h>
14 #include <linux/mmc/core.h>
15 #include <linux/dmaengine.h>
16 #include <linux/reset.h>
17 #include <linux/fault-inject.h>
18 #include <linux/hrtimer.h>
19 #include <linux/interrupt.h>
20 
21 enum dw_mci_state {
22 	STATE_IDLE = 0,
23 	STATE_SENDING_CMD,
24 	STATE_SENDING_DATA,
25 	STATE_DATA_BUSY,
26 	STATE_SENDING_STOP,
27 	STATE_DATA_ERROR,
28 	STATE_SENDING_CMD11,
29 	STATE_WAITING_CMD11_DONE,
30 };
31 
32 enum {
33 	EVENT_CMD_COMPLETE = 0,
34 	EVENT_XFER_COMPLETE,
35 	EVENT_DATA_COMPLETE,
36 	EVENT_DATA_ERROR,
37 };
38 
39 enum dw_mci_cookie {
40 	COOKIE_UNMAPPED,
41 	COOKIE_PRE_MAPPED,	/* mapped by pre_req() of dwmmc */
42 	COOKIE_MAPPED,		/* mapped by prepare_data() of dwmmc */
43 };
44 
45 struct mmc_data;
46 
47 enum {
48 	TRANS_MODE_PIO = 0,
49 	TRANS_MODE_IDMAC,
50 	TRANS_MODE_EDMAC
51 };
52 
53 struct dw_mci_dma_slave {
54 	struct dma_chan *ch;
55 	enum dma_transfer_direction direction;
56 };
57 
58 /**
59  * struct dw_mci - MMC controller state shared between all slots
60  * @lock: Spinlock protecting the queue and associated data.
61  * @irq_lock: Spinlock protecting the INTMASK setting.
62  * @regs: Pointer to MMIO registers.
63  * @fifo_reg: Pointer to MMIO registers for data FIFO
64  * @sg: Scatterlist entry currently being processed by PIO code, if any.
65  * @sg_miter: PIO mapping scatterlist iterator.
66  * @mrq: The request currently being processed on @slot,
67  *	or NULL if the controller is idle.
68  * @cmd: The command currently being sent to the card, or NULL.
69  * @data: The data currently being transferred, or NULL if no data
70  *	transfer is in progress.
71  * @stop_abort: The command currently prepared for stoping transfer.
72  * @prev_blksz: The former transfer blksz record.
73  * @timing: Record of current ios timing.
74  * @use_dma: Which DMA channel is in use for the current transfer, zero
75  *	denotes PIO mode.
76  * @using_dma: Whether DMA is in use for the current transfer.
77  * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
78  * @sg_dma: Bus address of DMA buffer.
79  * @sg_cpu: Virtual address of DMA buffer.
80  * @dma_ops: Pointer to platform-specific DMA callbacks.
81  * @cmd_status: Snapshot of SR taken upon completion of the current
82  * @ring_size: Buffer size for idma descriptors.
83  *	command. Only valid when EVENT_CMD_COMPLETE is pending.
84  * @dms: structure of slave-dma private data.
85  * @phy_regs: physical address of controller's register map
86  * @data_status: Snapshot of SR taken upon completion of the current
87  *	data transfer. Only valid when EVENT_DATA_COMPLETE or
88  *	EVENT_DATA_ERROR is pending.
89  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
90  *	to be sent.
91  * @dir_status: Direction of current transfer.
92  * @tasklet: Tasklet running the request state machine.
93  * @pending_events: Bitmask of events flagged by the interrupt handler
94  *	to be processed by the tasklet.
95  * @completed_events: Bitmask of events which the state machine has
96  *	processed.
97  * @state: Tasklet state.
98  * @queue: List of slots waiting for access to the controller.
99  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
100  *	rate and timeout calculations.
101  * @current_speed: Configured rate of the controller.
102  * @fifoth_val: The value of FIFOTH register.
103  * @verid: Denote Version ID.
104  * @dev: Device associated with the MMC controller.
105  * @pdata: Platform data associated with the MMC controller.
106  * @drv_data: Driver specific data for identified variant of the controller
107  * @priv: Implementation defined private data.
108  * @biu_clk: Pointer to bus interface unit clock instance.
109  * @ciu_clk: Pointer to card interface unit clock instance.
110  * @slot: Slots sharing this MMC controller.
111  * @fifo_depth: depth of FIFO.
112  * @data_addr_override: override fifo reg offset with this value.
113  * @wm_aligned: force fifo watermark equal with data length in PIO mode.
114  *	Set as true if alignment is needed.
115  * @data_shift: log2 of FIFO item size.
116  * @part_buf_start: Start index in part_buf.
117  * @part_buf_count: Bytes of partial data in part_buf.
118  * @part_buf: Simple buffer for partial fifo reads/writes.
119  * @push_data: Pointer to FIFO push function.
120  * @pull_data: Pointer to FIFO pull function.
121  * @vqmmc_enabled: Status of vqmmc, should be true or false.
122  * @irq_flags: The flags to be passed to request_irq.
123  * @irq: The irq value to be passed to request_irq.
124  * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
125  * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
126  * @cto_timer: Timer for broken command transfer over scheme.
127  * @dto_timer: Timer for broken data transfer over scheme.
128  *
129  * Locking
130  * =======
131  *
132  * @lock is a softirq-safe spinlock protecting @queue as well as
133  * @slot, @mrq and @state. These must always be updated
134  * at the same time while holding @lock.
135  * The @mrq field of struct dw_mci_slot is also protected by @lock,
136  * and must always be written at the same time as the slot is added to
137  * @queue.
138  *
139  * @irq_lock is an irq-safe spinlock protecting the INTMASK register
140  * to allow the interrupt handler to modify it directly.  Held for only long
141  * enough to read-modify-write INTMASK and no other locks are grabbed when
142  * holding this one.
143  *
144  * @pending_events and @completed_events are accessed using atomic bit
145  * operations, so they don't need any locking.
146  *
147  * None of the fields touched by the interrupt handler need any
148  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
149  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
150  * interrupts must be disabled and @data_status updated with a
151  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
152  * CMDRDY interrupt must be disabled and @cmd_status updated with a
153  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
154  * bytes_xfered field of @data must be written. This is ensured by
155  * using barriers.
156  */
157 struct dw_mci {
158 	spinlock_t		lock;
159 	spinlock_t		irq_lock;
160 	void __iomem		*regs;
161 	void __iomem		*fifo_reg;
162 	u32			data_addr_override;
163 	bool			wm_aligned;
164 
165 	struct scatterlist	*sg;
166 	struct sg_mapping_iter	sg_miter;
167 
168 	struct mmc_request	*mrq;
169 	struct mmc_command	*cmd;
170 	struct mmc_data		*data;
171 	struct mmc_command	stop_abort;
172 	unsigned int		prev_blksz;
173 	unsigned char		timing;
174 
175 	/* DMA interface members*/
176 	int			use_dma;
177 	int			using_dma;
178 	int			dma_64bit_address;
179 
180 	dma_addr_t		sg_dma;
181 	void			*sg_cpu;
182 	const struct dw_mci_dma_ops	*dma_ops;
183 	/* For idmac */
184 	unsigned int		ring_size;
185 
186 	/* For edmac */
187 	struct dw_mci_dma_slave *dms;
188 	/* Registers's physical base address */
189 	resource_size_t		phy_regs;
190 
191 	u32			cmd_status;
192 	u32			data_status;
193 	u32			stop_cmdr;
194 	u32			dir_status;
195 	struct tasklet_struct	tasklet;
196 	unsigned long		pending_events;
197 	unsigned long		completed_events;
198 	enum dw_mci_state	state;
199 	struct list_head	queue;
200 
201 	u32			bus_hz;
202 	u32			current_speed;
203 	u32			fifoth_val;
204 	u16			verid;
205 	struct device		*dev;
206 	struct dw_mci_board	*pdata;
207 	const struct dw_mci_drv_data	*drv_data;
208 	void			*priv;
209 	struct clk		*biu_clk;
210 	struct clk		*ciu_clk;
211 	struct dw_mci_slot	*slot;
212 
213 	/* FIFO push and pull */
214 	int			fifo_depth;
215 	int			data_shift;
216 	u8			part_buf_start;
217 	u8			part_buf_count;
218 	union {
219 		u16		part_buf16;
220 		u32		part_buf32;
221 		u64		part_buf;
222 	};
223 	void (*push_data)(struct dw_mci *host, void *buf, int cnt);
224 	void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
225 
226 	bool			vqmmc_enabled;
227 	unsigned long		irq_flags; /* IRQ flags */
228 	int			irq;
229 
230 	int			sdio_id0;
231 
232 	struct timer_list       cmd11_timer;
233 	struct timer_list       cto_timer;
234 	struct timer_list       dto_timer;
235 
236 #ifdef CONFIG_FAULT_INJECTION
237 	struct fault_attr	fail_data_crc;
238 	struct hrtimer		fault_timer;
239 #endif
240 };
241 
242 /* DMA ops for Internal/External DMAC interface */
243 struct dw_mci_dma_ops {
244 	/* DMA Ops */
245 	int (*init)(struct dw_mci *host);
246 	int (*start)(struct dw_mci *host, unsigned int sg_len);
247 	void (*complete)(void *host);
248 	void (*stop)(struct dw_mci *host);
249 	void (*cleanup)(struct dw_mci *host);
250 	void (*exit)(struct dw_mci *host);
251 };
252 
253 struct dma_pdata;
254 
255 /* Board platform data */
256 struct dw_mci_board {
257 	unsigned int bus_hz; /* Clock speed at the cclk_in pad */
258 
259 	u32 caps;	/* Capabilities */
260 	u32 caps2;	/* More capabilities */
261 	u32 pm_caps;	/* PM capabilities */
262 	/*
263 	 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
264 	 * but note that this may not be reliable after a bootloader has used
265 	 * it.
266 	 */
267 	unsigned int fifo_depth;
268 
269 	/* delay in mS before detecting cards after interrupt */
270 	u32 detect_delay_ms;
271 
272 	struct reset_control *rstc;
273 	struct dw_mci_dma_ops *dma_ops;
274 	struct dma_pdata *data;
275 };
276 
277 #define DW_MMC_240A		0x240a
278 #define DW_MMC_280A		0x280a
279 
280 #define SDMMC_CTRL		0x000
281 #define SDMMC_PWREN		0x004
282 #define SDMMC_CLKDIV		0x008
283 #define SDMMC_CLKSRC		0x00c
284 #define SDMMC_CLKENA		0x010
285 #define SDMMC_TMOUT		0x014
286 #define SDMMC_CTYPE		0x018
287 #define SDMMC_BLKSIZ		0x01c
288 #define SDMMC_BYTCNT		0x020
289 #define SDMMC_INTMASK		0x024
290 #define SDMMC_CMDARG		0x028
291 #define SDMMC_CMD		0x02c
292 #define SDMMC_RESP0		0x030
293 #define SDMMC_RESP1		0x034
294 #define SDMMC_RESP2		0x038
295 #define SDMMC_RESP3		0x03c
296 #define SDMMC_MINTSTS		0x040
297 #define SDMMC_RINTSTS		0x044
298 #define SDMMC_STATUS		0x048
299 #define SDMMC_FIFOTH		0x04c
300 #define SDMMC_CDETECT		0x050
301 #define SDMMC_WRTPRT		0x054
302 #define SDMMC_GPIO		0x058
303 #define SDMMC_TCBCNT		0x05c
304 #define SDMMC_TBBCNT		0x060
305 #define SDMMC_DEBNCE		0x064
306 #define SDMMC_USRID		0x068
307 #define SDMMC_VERID		0x06c
308 #define SDMMC_HCON		0x070
309 #define SDMMC_UHS_REG		0x074
310 #define SDMMC_RST_N		0x078
311 #define SDMMC_BMOD		0x080
312 #define SDMMC_PLDMND		0x084
313 #define SDMMC_DBADDR		0x088
314 #define SDMMC_IDSTS		0x08c
315 #define SDMMC_IDINTEN		0x090
316 #define SDMMC_DSCADDR		0x094
317 #define SDMMC_BUFADDR		0x098
318 #define SDMMC_CDTHRCTL		0x100
319 #define SDMMC_UHS_REG_EXT	0x108
320 #define SDMMC_DDR_REG		0x10c
321 #define SDMMC_ENABLE_SHIFT	0x110
322 #define SDMMC_DATA(x)		(x)
323 /*
324  * Registers to support idmac 64-bit address mode
325  */
326 #define SDMMC_DBADDRL		0x088
327 #define SDMMC_DBADDRU		0x08c
328 #define SDMMC_IDSTS64		0x090
329 #define SDMMC_IDINTEN64		0x094
330 #define SDMMC_DSCADDRL		0x098
331 #define SDMMC_DSCADDRU		0x09c
332 #define SDMMC_BUFADDRL		0x0A0
333 #define SDMMC_BUFADDRU		0x0A4
334 
335 /*
336  * Data offset is difference according to Version
337  * Lower than 2.40a : data register offest is 0x100
338  */
339 #define DATA_OFFSET		0x100
340 #define DATA_240A_OFFSET	0x200
341 
342 /* shift bit field */
343 #define _SBF(f, v)		((v) << (f))
344 
345 /* Control register defines */
346 #define SDMMC_CTRL_USE_IDMAC		BIT(25)
347 #define SDMMC_CTRL_CEATA_INT_EN		BIT(11)
348 #define SDMMC_CTRL_SEND_AS_CCSD		BIT(10)
349 #define SDMMC_CTRL_SEND_CCSD		BIT(9)
350 #define SDMMC_CTRL_ABRT_READ_DATA	BIT(8)
351 #define SDMMC_CTRL_SEND_IRQ_RESP	BIT(7)
352 #define SDMMC_CTRL_READ_WAIT		BIT(6)
353 #define SDMMC_CTRL_DMA_ENABLE		BIT(5)
354 #define SDMMC_CTRL_INT_ENABLE		BIT(4)
355 #define SDMMC_CTRL_DMA_RESET		BIT(2)
356 #define SDMMC_CTRL_FIFO_RESET		BIT(1)
357 #define SDMMC_CTRL_RESET		BIT(0)
358 /* Clock Enable register defines */
359 #define SDMMC_CLKEN_LOW_PWR		BIT(16)
360 #define SDMMC_CLKEN_ENABLE		BIT(0)
361 /* time-out register defines */
362 #define SDMMC_TMOUT_DATA(n)		_SBF(8, (n))
363 #define SDMMC_TMOUT_DATA_MSK		0xFFFFFF00
364 #define SDMMC_TMOUT_RESP(n)		((n) & 0xFF)
365 #define SDMMC_TMOUT_RESP_MSK		0xFF
366 /* card-type register defines */
367 #define SDMMC_CTYPE_8BIT		BIT(16)
368 #define SDMMC_CTYPE_4BIT		BIT(0)
369 #define SDMMC_CTYPE_1BIT		0
370 /* Interrupt status & mask register defines */
371 #define SDMMC_INT_SDIO(n)		BIT(16 + (n))
372 #define SDMMC_INT_EBE			BIT(15)
373 #define SDMMC_INT_ACD			BIT(14)
374 #define SDMMC_INT_SBE			BIT(13)
375 #define SDMMC_INT_HLE			BIT(12)
376 #define SDMMC_INT_FRUN			BIT(11)
377 #define SDMMC_INT_HTO			BIT(10)
378 #define SDMMC_INT_VOLT_SWITCH		BIT(10) /* overloads bit 10! */
379 #define SDMMC_INT_DRTO			BIT(9)
380 #define SDMMC_INT_RTO			BIT(8)
381 #define SDMMC_INT_DCRC			BIT(7)
382 #define SDMMC_INT_RCRC			BIT(6)
383 #define SDMMC_INT_RXDR			BIT(5)
384 #define SDMMC_INT_TXDR			BIT(4)
385 #define SDMMC_INT_DATA_OVER		BIT(3)
386 #define SDMMC_INT_CMD_DONE		BIT(2)
387 #define SDMMC_INT_RESP_ERR		BIT(1)
388 #define SDMMC_INT_CD			BIT(0)
389 #define SDMMC_INT_ERROR			0xbfc2
390 /* Command register defines */
391 #define SDMMC_CMD_START			BIT(31)
392 #define SDMMC_CMD_USE_HOLD_REG	BIT(29)
393 #define SDMMC_CMD_VOLT_SWITCH		BIT(28)
394 #define SDMMC_CMD_CCS_EXP		BIT(23)
395 #define SDMMC_CMD_CEATA_RD		BIT(22)
396 #define SDMMC_CMD_UPD_CLK		BIT(21)
397 #define SDMMC_CMD_INIT			BIT(15)
398 #define SDMMC_CMD_STOP			BIT(14)
399 #define SDMMC_CMD_PRV_DAT_WAIT		BIT(13)
400 #define SDMMC_CMD_SEND_STOP		BIT(12)
401 #define SDMMC_CMD_STRM_MODE		BIT(11)
402 #define SDMMC_CMD_DAT_WR		BIT(10)
403 #define SDMMC_CMD_DAT_EXP		BIT(9)
404 #define SDMMC_CMD_RESP_CRC		BIT(8)
405 #define SDMMC_CMD_RESP_LONG		BIT(7)
406 #define SDMMC_CMD_RESP_EXP		BIT(6)
407 #define SDMMC_CMD_INDX(n)		((n) & 0x1F)
408 /* Status register defines */
409 #define SDMMC_GET_FCNT(x)		(((x)>>17) & 0x1FFF)
410 #define SDMMC_STATUS_DMA_REQ		BIT(31)
411 #define SDMMC_STATUS_BUSY		BIT(9)
412 /* FIFOTH register defines */
413 #define SDMMC_SET_FIFOTH(m, r, t)	(((m) & 0x7) << 28 | \
414 					 ((r) & 0xFFF) << 16 | \
415 					 ((t) & 0xFFF))
416 /* HCON register defines */
417 #define DMA_INTERFACE_IDMA		(0x0)
418 #define DMA_INTERFACE_DWDMA		(0x1)
419 #define DMA_INTERFACE_GDMA		(0x2)
420 #define DMA_INTERFACE_NODMA		(0x3)
421 #define SDMMC_GET_TRANS_MODE(x)		(((x)>>16) & 0x3)
422 #define SDMMC_GET_SLOT_NUM(x)		((((x)>>1) & 0x1F) + 1)
423 #define SDMMC_GET_HDATA_WIDTH(x)	(((x)>>7) & 0x7)
424 #define SDMMC_GET_ADDR_CONFIG(x)	(((x)>>27) & 0x1)
425 /* Internal DMAC interrupt defines */
426 #define SDMMC_IDMAC_INT_AI		BIT(9)
427 #define SDMMC_IDMAC_INT_NI		BIT(8)
428 #define SDMMC_IDMAC_INT_CES		BIT(5)
429 #define SDMMC_IDMAC_INT_DU		BIT(4)
430 #define SDMMC_IDMAC_INT_FBE		BIT(2)
431 #define SDMMC_IDMAC_INT_RI		BIT(1)
432 #define SDMMC_IDMAC_INT_TI		BIT(0)
433 /* Internal DMAC bus mode bits */
434 #define SDMMC_IDMAC_ENABLE		BIT(7)
435 #define SDMMC_IDMAC_FB			BIT(1)
436 #define SDMMC_IDMAC_SWRESET		BIT(0)
437 /* H/W reset */
438 #define SDMMC_RST_HWACTIVE		0x1
439 /* Version ID register define */
440 #define SDMMC_GET_VERID(x)		((x) & 0xFFFF)
441 /* Card read threshold */
442 #define SDMMC_SET_THLD(v, x)		(((v) & 0xFFF) << 16 | (x))
443 #define SDMMC_CARD_WR_THR_EN		BIT(2)
444 #define SDMMC_CARD_RD_THR_EN		BIT(0)
445 /* UHS-1 register defines */
446 #define SDMMC_UHS_DDR			BIT(16)
447 #define SDMMC_UHS_18V			BIT(0)
448 /* DDR register defines */
449 #define SDMMC_DDR_HS400			BIT(31)
450 /* Enable shift register defines */
451 #define SDMMC_ENABLE_PHASE		BIT(0)
452 /* All ctrl reset bits */
453 #define SDMMC_CTRL_ALL_RESET_FLAGS \
454 	(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
455 
456 /* FIFO register access macros. These should not change the data endian-ness
457  * as they are written to memory to be dealt with by the upper layers
458  */
459 #define mci_fifo_readw(__reg)	__raw_readw(__reg)
460 #define mci_fifo_readl(__reg)	__raw_readl(__reg)
461 #define mci_fifo_readq(__reg)	__raw_readq(__reg)
462 
463 #define mci_fifo_writew(__value, __reg)	__raw_writew(__reg, __value)
464 #define mci_fifo_writel(__value, __reg)	__raw_writel(__reg, __value)
465 #define mci_fifo_writeq(__value, __reg)	__raw_writeq(__reg, __value)
466 
467 /* Register access macros */
468 #define mci_readl(dev, reg)			\
469 	readl_relaxed((dev)->regs + SDMMC_##reg)
470 #define mci_writel(dev, reg, value)			\
471 	writel_relaxed((value), (dev)->regs + SDMMC_##reg)
472 
473 /* 16-bit FIFO access macros */
474 #define mci_readw(dev, reg)			\
475 	readw_relaxed((dev)->regs + SDMMC_##reg)
476 #define mci_writew(dev, reg, value)			\
477 	writew_relaxed((value), (dev)->regs + SDMMC_##reg)
478 
479 /* 64-bit FIFO access macros */
480 #ifdef readq
481 #define mci_readq(dev, reg)			\
482 	readq_relaxed((dev)->regs + SDMMC_##reg)
483 #define mci_writeq(dev, reg, value)			\
484 	writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
485 #else
486 /*
487  * Dummy readq implementation for architectures that don't define it.
488  *
489  * We would assume that none of these architectures would configure
490  * the IP block with a 64bit FIFO width, so this code will never be
491  * executed on those machines. Defining these macros here keeps the
492  * rest of the code free from ifdefs.
493  */
494 #define mci_readq(dev, reg)			\
495 	(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
496 #define mci_writeq(dev, reg, value)			\
497 	(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
498 
499 #define __raw_writeq(__value, __reg) \
500 	(*(volatile u64 __force *)(__reg) = (__value))
501 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
502 #endif
503 
504 extern int dw_mci_probe(struct dw_mci *host);
505 extern void dw_mci_remove(struct dw_mci *host);
506 #ifdef CONFIG_PM
507 extern int dw_mci_runtime_suspend(struct device *device);
508 extern int dw_mci_runtime_resume(struct device *device);
509 #endif
510 
511 /**
512  * struct dw_mci_slot - MMC slot state
513  * @mmc: The mmc_host representing this slot.
514  * @host: The MMC controller this slot is using.
515  * @ctype: Card type for this slot.
516  * @mrq: mmc_request currently being processed or waiting to be
517  *	processed, or NULL when the slot is idle.
518  * @queue_node: List node for placing this node in the @queue list of
519  *	&struct dw_mci.
520  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
521  * @__clk_old: The last clock value that was requested from core.
522  *	Keeping track of this helps us to avoid spamming the console.
523  * @flags: Random state bits associated with the slot.
524  * @id: Number of this slot.
525  * @sdio_id: Number of this slot in the SDIO interrupt registers.
526  */
527 struct dw_mci_slot {
528 	struct mmc_host		*mmc;
529 	struct dw_mci		*host;
530 
531 	u32			ctype;
532 
533 	struct mmc_request	*mrq;
534 	struct list_head	queue_node;
535 
536 	unsigned int		clock;
537 	unsigned int		__clk_old;
538 
539 	unsigned long		flags;
540 #define DW_MMC_CARD_PRESENT	0
541 #define DW_MMC_CARD_NEED_INIT	1
542 #define DW_MMC_CARD_NO_LOW_PWR	2
543 #define DW_MMC_CARD_NO_USE_HOLD 3
544 #define DW_MMC_CARD_NEEDS_POLL	4
545 	int			id;
546 	int			sdio_id;
547 };
548 
549 /**
550  * dw_mci driver data - dw-mshc implementation specific driver data.
551  * @caps: mmc subsystem specified capabilities of the controller(s).
552  * @num_caps: number of capabilities specified by @caps.
553  * @init: early implementation specific initialization.
554  * @set_ios: handle bus specific extensions.
555  * @parse_dt: parse implementation specific device tree properties.
556  * @execute_tuning: implementation specific tuning procedure.
557  *
558  * Provide controller implementation specific extensions. The usage of this
559  * data structure is fully optional and usage of each member in this structure
560  * is optional as well.
561  */
562 struct dw_mci_drv_data {
563 	unsigned long	*caps;
564 	u32		num_caps;
565 	int		(*init)(struct dw_mci *host);
566 	void		(*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
567 	int		(*parse_dt)(struct dw_mci *host);
568 	int		(*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
569 	int		(*prepare_hs400_tuning)(struct dw_mci *host,
570 						struct mmc_ios *ios);
571 	int		(*switch_voltage)(struct mmc_host *mmc,
572 					  struct mmc_ios *ios);
573 };
574 #endif /* _DW_MMC_H_ */
575