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Searched refs:SET0 (Results 1 – 3 of 3) sorted by relevance

/linux/arch/mips/loongson64/
A Dsmp.c204 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()
206 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()
208 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0); in ipi_set0_regs_init()
210 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0); in ipi_set0_regs_init()
212 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()
214 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()
216 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0); in ipi_set0_regs_init()
218 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0); in ipi_set0_regs_init()
220 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0); in ipi_set0_regs_init()
222 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0); in ipi_set0_regs_init()
[all …]
A Dsmp.h23 #define SET0 0x08 macro
/linux/Documentation/devicetree/bindings/pci/
A Dmediatek-pcie-gen3.yaml40 (MSI SET0) (MSI SET1) ... (MSI SET7)

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