Searched refs:SKL_DPLL0 (Results 1 – 2 of 2) sorted by relevance
884 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | in skl_dpll0_update()885 DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_update()886 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != in skl_dpll0_update()887 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) in skl_dpll0_update()890 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { in skl_dpll0_update()891 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): in skl_dpll0_update()902 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); in skl_dpll0_update()1007 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | in skl_dpll0_enable()1008 DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_enable()1009 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), in skl_dpll0_enable()[all …]
364 #define SKL_DPLL0 0 macro
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