1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* linux/amba/pl093.h
3  *
4  * Copyright (c) 2008 Simtec Electronics
5  *	http://armlinux.simtec.co.uk/
6  *	Ben Dooks <ben@simtec.co.uk>
7  *
8  * AMBA PL093 SSMC (synchronous static memory controller)
9  *  See DDI0236.pdf (r0p4) for more details
10 */
11 
12 #define SMB_BANK(x)	((x) * 0x20) /* each bank control set is 0x20 apart */
13 
14 /* Offsets for SMBxxxxRy registers */
15 
16 #define SMBIDCYR	(0x00)
17 #define SMBWSTRDR	(0x04)
18 #define SMBWSTWRR	(0x08)
19 #define SMBWSTOENR	(0x0C)
20 #define SMBWSTWENR	(0x10)
21 #define SMBCR		(0x14)
22 #define SMBSR		(0x18)
23 #define SMBWSTBRDR	(0x1C)
24 
25 /* Masks for SMB registers */
26 #define IDCY_MASK	(0xf)
27 #define WSTRD_MASK	(0xf)
28 #define WSTWR_MASK	(0xf)
29 #define WSTOEN_MASK	(0xf)
30 #define WSTWEN_MASK	(0xf)
31 
32 /* Notes from datasheet:
33  *	WSTOEN <= WSTRD
34  *	WSTWEN <= WSTWR
35  *
36  * WSTOEN is not used with nWAIT
37  */
38 
39 /* SMBCR bit definitions */
40 #define SMBCR_BIWRITEEN		(1 << 21)
41 #define SMBCR_ADDRVALIDWRITEEN	(1 << 20)
42 #define SMBCR_SYNCWRITE		(1 << 17)
43 #define SMBCR_BMWRITE		(1 << 16)
44 #define SMBCR_WRAPREAD		(1 << 14)
45 #define SMBCR_BIREADEN		(1 << 13)
46 #define SMBCR_ADDRVALIDREADEN	(1 << 12)
47 #define SMBCR_SYNCREAD		(1 << 9)
48 #define SMBCR_BMREAD		(1 << 8)
49 #define SMBCR_SMBLSPOL		(1 << 6)
50 #define SMBCR_WP		(1 << 3)
51 #define SMBCR_WAITEN		(1 << 2)
52 #define SMBCR_WAITPOL		(1 << 1)
53 #define SMBCR_RBLE		(1 << 0)
54 
55 #define SMBCR_BURSTLENWRITE_MASK	(3 << 18)
56 #define SMBCR_BURSTLENWRITE_4		(0 << 18)
57 #define SMBCR_BURSTLENWRITE_8		(1 << 18)
58 #define SMBCR_BURSTLENWRITE_RESERVED	(2 << 18)
59 #define SMBCR_BURSTLENWRITE_CONTINUOUS	(3 << 18)
60 
61 #define SMBCR_BURSTLENREAD_MASK		(3 << 10)
62 #define SMBCR_BURSTLENREAD_4		(0 << 10)
63 #define SMBCR_BURSTLENREAD_8		(1 << 10)
64 #define SMBCR_BURSTLENREAD_16		(2 << 10)
65 #define SMBCR_BURSTLENREAD_CONTINUOUS	(3 << 10)
66 
67 #define SMBCR_MW_MASK			(3 << 4)
68 #define SMBCR_MW_8BIT			(0 << 4)
69 #define SMBCR_MW_16BIT			(1 << 4)
70 #define SMBCR_MW_M32BIT			(2 << 4)
71 
72 /* SSMC status registers */
73 #define SSMCCSR		(0x200)
74 #define SSMCCR		(0x204)
75 #define SSMCITCR	(0x208)
76 #define SSMCITIP	(0x20C)
77 #define SSMCITIOP	(0x210)
78