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Searched refs:SSI1 (Results 1 – 11 of 11) sorted by relevance

/linux/arch/sh/kernel/cpu/sh4/
A Dsetup-sh7760.c24 SSI0, SSI1, enumerator
53 INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
90 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
109 { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
/linux/arch/sh/kernel/cpu/sh4a/
A Dsetup-sh7763.c245 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3, enumerator
288 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
311 LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
326 { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
A Dsetup-sh7785.c383 SSI0, SSI1, enumerator
425 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
453 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
474 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
A Dsetup-sh7734.c308 SSI0, SSI1, SSI2, SSI3, enumerator
384 INTC_VECT(SSI1, 0x6E0),
439 INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3),
A Dsetup-sh7786.c491 SSI0, SSI1, SSI2, SSI3, enumerator
534 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
607 DU, SSI0, SSI1, SSI2, SSI3,
646 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
/linux/Documentation/devicetree/bindings/sound/
A Drenesas,rsnd.txt40 Capture: [MEM] <- [DVC1] <- [SRC3] <- [SSIU1/SSI1] <- [codec]
236 This is example if SSI1 want to share WS pin with SSI0
245 This is example of SSI0/SSI1/SSI2 (= for 6ch)
A Dfsl,ssi.txt13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
75 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
A Drenesas,rsnd.yaml318 <&mstp10_clks 1014>, <&mstp10_clks 1015>, /* SSI1, SSI0 */
/linux/Documentation/devicetree/bindings/interrupt-controller/
A Dcirrus,clps711x-intc.txt27 15: SSEOTI SSI1 end of transfer
/linux/arch/arm/boot/dts/
A Dimx53-voipac-bsb.dts109 pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */
/linux/drivers/spi/
A DKconfig248 master mode interface (SSI1) for CLPS711X-based CPUs.

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