Searched refs:SSPP_DMA1 (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/msm/disp/mdp5/ |
| A D | mdp5_cfg.c | 29 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
118 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
207 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
459 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
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| A D | mdp5_ctl.c | 299 case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage); in mdp_ctl_blend_mask()
322 case SSPP_DMA1: return MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3; in mdp_ctl_blend_ext_mask()
450 case SSPP_DMA1: return MDP5_CTL_FLUSH_DMA1; in mdp_ctl_flush_mask_pipe()
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| A D | mdp5.xml.h | 84 SSPP_DMA1 = 8, enumerator
558 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]); in __offset_PIPE()
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| A D | mdp5_kms.c | 724 SSPP_DMA0, SSPP_DMA1, in hwpipe_init() enumerator
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_hw_top.c | 147 status->sspp[SSPP_DMA1] = (value >> 22) & 0x3; in dpu_hw_get_danger_status()
244 status->sspp[SSPP_DMA1] = (value >> 22) & 0x1; in dpu_hw_get_safe_status()
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| A D | dpu_hw_ctl.c | 174 case SSPP_DMA1: in dpu_hw_ctl_get_bitmask_sspp()
450 case SSPP_DMA1: in dpu_hw_ctl_setup_blendstage()
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| A D | dpu_hw_catalog.c | 537 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
553 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
579 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
592 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
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| A D | dpu_hw_mdss.h | 119 SSPP_DMA1, enumerator
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