Searched refs:SSPP_VIG1 (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/msm/disp/mdp5/ |
| A D | mdp5_cfg.c | 28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
117 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
205 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
457 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
676 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
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| A D | mdp5_ctl.c | 293 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage); in mdp_ctl_blend_mask()
316 case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3; in mdp_ctl_blend_ext_mask()
444 case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1; in mdp_ctl_flush_mask_pipe()
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| A D | mdp5.xml.h | 78 SSPP_VIG1 = 2, enumerator
552 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]); in __offset_PIPE()
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| A D | mdp5_kms.c | 721 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_hw_top.c | 139 status->sspp[SSPP_VIG1] = (value >> 6) & 0x3; in dpu_hw_get_danger_status()
236 status->sspp[SSPP_VIG1] = (value >> 6) & 0x1; in dpu_hw_get_safe_status()
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| A D | dpu_hw_ctl.c | 150 case SSPP_VIG1: in dpu_hw_ctl_get_bitmask_sspp()
402 case SSPP_VIG1: in dpu_hw_ctl_setup_blendstage()
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| A D | dpu_hw_mdss.h | 111 SSPP_VIG1, enumerator
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| A D | dpu_hw_catalog.c | 529 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
571 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
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