Searched refs:SW_RESET (Results 1 – 12 of 12) sorted by relevance
/linux/drivers/clk/qcom/ |
A D | gdsc.h | 50 #define SW_RESET BIT(3) macro
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A D | gpucc-sdm660.c | 257 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
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A D | gpucc-msm8998.c | 272 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
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A D | gdsc.c | 259 if (sc->flags & SW_RESET) { in _gdsc_enable()
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/linux/drivers/watchdog/ |
A D | asm9260_wdt.c | 50 SW_RESET, enumerator 277 priv->mode = SW_RESET; in asm9260_wdt_get_dt_mode()
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/linux/sound/soc/tegra/ |
A D | tegra210_admaif.h | 67 #define SW_RESET 1 macro
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A D | tegra210_admaif.c | 384 regmap_update_bits(admaif->regmap, reset_reg, SW_RESET_MASK, SW_RESET); in tegra_admaif_stop() 388 !(val & SW_RESET_MASK & SW_RESET), in tegra_admaif_stop()
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/linux/arch/arm/boot/dts/ |
A D | imx6qp-prtwd3.dts | 277 "", "", "", "", "", "SW_RESET", "", "",
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/linux/drivers/net/wireless/intel/ipw2x00/ |
A D | ipw2100.h | 301 SW_RESET, enumerator
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/linux/drivers/phy/qualcomm/ |
A D | phy-qcom-qmp.c | 28 #define SW_RESET BIT(0) macro 4199 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); in qcom_qmp_phy_serdes_init() 4759 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); in qcom_qmp_phy_com_init() 4808 SW_RESET); in qcom_qmp_phy_com_exit() 4969 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qcom_qmp_phy_power_on() 5014 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qcom_qmp_phy_power_off()
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/linux/drivers/net/dsa/microchip/ |
A D | ksz9477_reg.h | 168 #define SW_RESET BIT(1) macro
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A D | ksz9477.c | 202 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); in ksz9477_reset_switch()
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