Searched refs:SYSTEM_CONTROL_REG_BASE (Results 1 – 1 of 1) sorted by relevance
31 #define SYSTEM_CONTROL_REG_BASE 0x0880 macro70 #define MUX_MODE_CTRL (SYSTEM_CONTROL_REG_BASE + 0x00)86 #define INTERNAL_RST (SYSTEM_CONTROL_REG_BASE + 0x04)87 #define PERIPHERAL_CTRL (SYSTEM_CONTROL_REG_BASE + 0x08)88 #define GPIO_0to7_CTRL (SYSTEM_CONTROL_REG_BASE + 0x0C)89 #define GPIO_8to15_CTRL (SYSTEM_CONTROL_REG_BASE + 0x10)90 #define GPIO_16to24_CTRL (SYSTEM_CONTROL_REG_BASE + 0x14)91 #define GPIO_INT_SRC_CFG (SYSTEM_CONTROL_REG_BASE + 0x18)92 #define SYS_BUF_STATUS (SYSTEM_CONTROL_REG_BASE + 0x1C)93 #define PCIE_IP_REG_ACS (SYSTEM_CONTROL_REG_BASE + 0x20)[all …]
Completed in 8 milliseconds