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Searched refs:TEGRA20_CLK_CDEV1 (Results 1 – 12 of 12) sorted by relevance

/linux/include/dt-bindings/clock/
A Dtegra20-car.h116 #define TEGRA20_CLK_CDEV1 94 macro
/linux/arch/arm/boot/dts/
A Dtegra20-plutux.dts59 <&tegra_car TEGRA20_CLK_CDEV1>;
A Dtegra20-tec.dts68 <&tegra_car TEGRA20_CLK_CDEV1>;
A Dtegra20-medcom-wide.dts91 <&tegra_car TEGRA20_CLK_CDEV1>;
A Dtegra20-trimslice.dts454 <&tegra_car TEGRA20_CLK_CDEV1>;
A Dtegra20-paz00.dts655 <&tegra_car TEGRA20_CLK_CDEV1>;
A Dtegra20-ventana.dts720 <&tegra_car TEGRA20_CLK_CDEV1>;
A Dtegra20-colibri.dtsi740 <&tegra_car TEGRA20_CLK_CDEV1>;
A Dtegra20-harmony.dts759 <&tegra_car TEGRA20_CLK_CDEV1>;
A Dtegra20-seaboard.dts918 <&tegra_car TEGRA20_CLK_CDEV1>;
A Dtegra20-acer-a500-picasso.dts1030 <&tegra_car TEGRA20_CLK_CDEV1>;
/linux/drivers/clk/tegra/
A Dclk-tegra20.c460 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
835 clks[TEGRA20_CLK_CDEV1] = clk; in tegra20_periph_clk_init()
1099 if (clkspec->args[0] == TEGRA20_CLK_CDEV1 || in tegra20_clk_src_onecell_get()

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