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Searched refs:TEGRA20_CLK_PLL_A_OUT0 (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/clk/tegra/
A Dclk-tegra20.c432 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
687 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; in tegra20_pll_init()
1036 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
1037 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1038 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
/linux/include/dt-bindings/clock/
A Dtegra20-car.h136 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/linux/arch/arm/boot/dts/
A Dtegra20-plutux.dts58 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
A Dtegra20-tec.dts67 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
A Dtegra20-medcom-wide.dts90 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
A Dtegra20-trimslice.dts453 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
A Dtegra20-paz00.dts654 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
A Dtegra20-ventana.dts719 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
A Dtegra20-colibri.dtsi739 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
A Dtegra20-harmony.dts758 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
A Dtegra20-seaboard.dts917 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
A Dtegra20-acer-a500-picasso.dts1029 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,

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