Searched refs:TSB (Results 1 – 5 of 5) sorted by relevance
| /linux/arch/sparc/include/asm/ |
| A D | tsb.h | 77 #define TSB_LOAD_QUAD(TSB, REG) \ argument
86 661: lduwa [TSB] ASI_N, REG; \
92 #define TSB_LOAD_TAG(TSB, REG) \ argument
93 661: ldxa [TSB] ASI_N, REG; \
96 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
121 99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
131 #define TSB_WRITE(TSB, TTE, TAG) \ argument
132 add TSB, 0x8, TSB; \
133 TSB_STORE(TSB, TTE); \
134 sub TSB, 0x8, TSB; \
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| /linux/arch/sparc/kernel/ |
| A D | dtlb_miss.S | 3 ldxa [%g0] ASI_DMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
9 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
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| A D | itlb_miss.S | 3 ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
9 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
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| /linux/arch/arm64/ |
| A D | Kconfig | 713 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
719 Affected cores may fail to flush the trace data on a TSB instruction, when
723 Workaround is to issue two TSB consecutively on affected cores.
728 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
734 Affected cores may fail to flush the trace data on a TSB instruction, when
738 Workaround is to issue two TSB consecutively on affected cores.
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| /linux/Documentation/sparc/oradax/ |
| A D | dax-hv-api.txt | 237 …dresses used in the CCB must have translation entries present in either the TLB or a configured TSB
1121 must be present in either the TLB or an active TSB to be processed. The translation context for vir…
1231 or TSB contents. The submission may be retried after adding the required
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