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Searched refs:TxINT_ENAB (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/net/wan/
A Dz85230.c212 1, EXT_INT_ENAB | TxINT_ENAB | INT_ALL_Rx,
234 1, EXT_INT_ENAB | TxINT_ENAB | INT_ALL_Rx,
741 c->regs[R1] |= TxINT_ENAB; in z8530_sync_open()
838 c->regs[R1] &= ~TxINT_ENAB; in z8530_sync_dma_open()
847 c->regs[R1] &= ~TxINT_ENAB; in z8530_sync_dma_open()
1017 c->regs[R1] &= ~TxINT_ENAB; in z8530_sync_txdma_open()
A Dz85230.h61 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
/linux/drivers/tty/serial/
A Dzs.c459 zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB); in zs_stop_rx()
786 zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB; in zs_startup()
1159 if (txint & TxINT_ENAB) { in zs_console_write()
1160 zport->regs[1] = txint & ~TxINT_ENAB; in zs_console_write()
1179 if (txint & TxINT_ENAB) { in zs_console_write()
1180 zport->regs[1] |= TxINT_ENAB; in zs_console_write()
A Dzs.h92 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
A Dsunzilog.h64 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
A Dip22zilog.h72 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
A Dip22zilog.c178 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); in __load_zsregs()
728 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in __ip22zilog_startup()
789 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in ip22zilog_shutdown()
1140 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in ip22zilog_prepare()
A Dsunzilog.c197 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); in __load_zsregs()
793 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in __sunzilog_startup()
854 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in sunzilog_shutdown()
1347 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in sunzilog_init_hw()
1363 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in sunzilog_init_hw()
A Dpmac_zilog.h161 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
A Dpmac_zilog.c132 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); in pmz_load_zsregs()
206 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB; in pmz_interrupt_control()
210 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in pmz_interrupt_control()
1966 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); in pmz_console_write()
/linux/drivers/net/hamradio/
A Dz8530.h40 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
A Dscc.c878 or(scc,R1,INT_ALL_Rx|TxINT_ENAB|EXT_INT_ENAB); /* enable interrupts */ in init_channel()
916 or(scc, R1, TxINT_ENAB); /* t_maxkeyup may have reset these */ in scc_key_trx()
1252 cl(scc, R1, TxINT_ENAB); /* force an ABORT, but don't */ in t_maxkeyup()
A Ddmascc.c1000 EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB); in tx_on()

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