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Searched refs:UIC_ARG_MIB_SEL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/scsi/ufs/
A Dtc-dwc-g210.c38 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14, in tc_dwc_g210_setup_40bit_rmmi()
46 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4, in tc_dwc_g210_setup_40bit_rmmi()
48 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_40bit_rmmi()
52 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_40bit_rmmi()
56 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16, in tc_dwc_g210_setup_40bit_rmmi()
62 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
66 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28, in tc_dwc_g210_setup_40bit_rmmi()
68 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E, in tc_dwc_g210_setup_40bit_rmmi()
70 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f, in tc_dwc_g210_setup_40bit_rmmi()
72 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f, in tc_dwc_g210_setup_40bit_rmmi()
[all …]
A Dufs-hisi.c34 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); in ufs_hisi_check_hibern8()
51 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); in ufs_hisi_check_hibern8()
146 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
148 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2); in ufs_hisi_link_startup_pre_change()
150 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
154 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
164 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
170 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB); in ufs_hisi_link_startup_pre_change()
172 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB); in ufs_hisi_link_startup_pre_change()
174 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1); in ufs_hisi_link_startup_pre_change()
[all …]
A Dufs-exynos.c329 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); in exynos7_ufs_pre_link()
351 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), in exynos7_ufs_post_link()
633 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
636 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
639 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
642 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
659 UIC_ARG_MIB_SEL(RX_MIN_ACTIVATETIME_CAP, in exynos_ufs_config_phy_cap_attr()
664 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i), in exynos_ufs_config_phy_cap_attr()
671 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, in exynos_ufs_config_phy_cap_attr()
677 UIC_ARG_MIB_SEL( in exynos_ufs_config_phy_cap_attr()
[all …]
A Dufshci.h242 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ macro
244 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
A Dufs-qcom.c208 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, in ufs_qcom_check_hibern8()
224 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, in ufs_qcom_check_hibern8()
A Dufs-mediatek.c815 UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0), in ufs_mtk_unipro_set_lpm()
A Dufshcd.c4063 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); in ufshcd_uic_change_pwr_mode()
4623 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, in ufshcd_disable_tx_lcc()
4628 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, in ufshcd_disable_tx_lcc()
7673 UIC_ARG_MIB_SEL( in ufshcd_tune_pa_tactivate()
7709 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY, in ufshcd_tune_pa_hibern8time()
7716 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY, in ufshcd_tune_pa_hibern8time()

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