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Searched refs:VAL (Results 1 – 25 of 58) sorted by relevance

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/linux/arch/arm64/kernel/
A Dhw_breakpoint.c61 AARCH64_DBG_READ(N, REG, VAL); \
66 AARCH64_DBG_WRITE(N, REG, VAL); \
70 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
71 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
72 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
73 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
74 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
75 READ_WB_REG_CASE(OFF, 5, REG, VAL); \
76 READ_WB_REG_CASE(OFF, 6, REG, VAL); \
85 READ_WB_REG_CASE(OFF, 15, REG, VAL)
[all …]
/linux/arch/arm/kernel/
A Dhw_breakpoint.c59 READ_WB_REG_CASE(OP2, 0, VAL); \
60 READ_WB_REG_CASE(OP2, 1, VAL); \
61 READ_WB_REG_CASE(OP2, 2, VAL); \
62 READ_WB_REG_CASE(OP2, 3, VAL); \
63 READ_WB_REG_CASE(OP2, 4, VAL); \
64 READ_WB_REG_CASE(OP2, 5, VAL); \
65 READ_WB_REG_CASE(OP2, 6, VAL); \
66 READ_WB_REG_CASE(OP2, 7, VAL); \
67 READ_WB_REG_CASE(OP2, 8, VAL); \
74 READ_WB_REG_CASE(OP2, 15, VAL)
[all …]
/linux/arch/arm64/include/asm/
A Dbarrier.h176 __unqual_scalar_typeof(*ptr) VAL; \
178 VAL = READ_ONCE(*__PTR); \
181 __cmpwait_relaxed(__PTR, VAL); \
183 (typeof(*ptr))VAL; \
189 __unqual_scalar_typeof(*ptr) VAL; \
191 VAL = smp_load_acquire(__PTR); \
194 __cmpwait_relaxed(__PTR, VAL); \
196 (typeof(*ptr))VAL; \
A Dhw_breakpoint.h99 #define AARCH64_DBG_READ(N, REG, VAL) do {\ argument
100 VAL = read_sysreg(dbg##REG##N##_el1);\
103 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ argument
104 write_sysreg(VAL, dbg##REG##N##_el1);\
/linux/tools/include/uapi/linux/
A Dbtf.h90 #define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24) argument
91 #define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16) argument
92 #define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff) argument
/linux/include/uapi/linux/
A Dbtf.h90 #define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24) argument
91 #define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16) argument
92 #define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff) argument
/linux/drivers/net/ethernet/qlogic/qlcnic/
A Dqlcnic_hdr.h641 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) argument
642 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) argument
643 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) argument
644 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) argument
645 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) argument
647 #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4))) argument
648 #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4)) argument
678 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
A Dqlcnic_83xx_hw.h405 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) argument
406 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2)) argument
/linux/drivers/watchdog/
A Dit87_wdt.c40 #define VAL 0x2f macro
123 outb(0x02, VAL); in superio_exit()
130 outb(ldn, VAL); in superio_select()
136 return inb(VAL); in superio_inb()
142 outb(val, VAL); in superio_outb()
149 val = inb(VAL) << 8; in superio_inw()
151 val |= inb(VAL); in superio_inw()
A Dit8712f_wdt.c57 #define VAL 0x2f /* The value to read/write */ macro
95 return inb(VAL); in superio_inb()
101 outb(val, VAL); in superio_outb()
108 val = inb(VAL) << 8; in superio_inw()
110 val |= inb(VAL); in superio_inw()
117 outb(ldn, VAL); in superio_select()
138 outb(0x02, VAL); in superio_exit()
/linux/drivers/net/ethernet/qlogic/netxen/
A Dnetxen_nic_hdr.h950 #define NETXEN_DIMM_MEMTYPE(VAL) ((VAL >> 3) & 0xf) argument
951 #define NETXEN_DIMM_NUMROWS(VAL) ((VAL >> 7) & 0xf) argument
952 #define NETXEN_DIMM_NUMCOLS(VAL) ((VAL >> 11) & 0xf) argument
953 #define NETXEN_DIMM_NUMRANKS(VAL) ((VAL >> 15) & 0x3) argument
954 #define NETXEN_DIMM_DATAWIDTH(VAL) ((VAL >> 18) & 0x3) argument
955 #define NETXEN_DIMM_NUMBANKS(VAL) ((VAL >> 21) & 0xf) argument
956 #define NETXEN_DIMM_TYPE(VAL) ((VAL >> 25) & 0x3f) argument
991 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
/linux/arch/arm/include/asm/
A Dhw_breakpoint.h109 #define ARM_DBG_READ(N, M, OP2, VAL) do {\ argument
110 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
113 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ argument
114 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
/linux/tools/testing/selftests/ntb/
A Dntb_test.sh266 VAL=$RANDOM
267 write_file "$VAL" "$LOC/spad$i"
270 if [[ "$VAL" -ne "$RVAL" ]]; then
271 echo "Scratchpad $i value $RVAL doesn't match $VAL" >&2
300 VAL=$RANDOM
301 write_file "$VAL" "$LOC/msg$i"
304 if [[ "$VAL" -ne "${RVAL%%<-*}" ]]; then
305 echo "Message $i value $RVAL doesn't match $VAL" >&2
/linux/drivers/gpio/
A Dgpio-it87.c38 #define VAL 0x2f macro
95 outb(0x02, VAL); in superio_exit()
102 outb(ldn, VAL); in superio_select()
108 return inb(VAL); in superio_inb()
114 outb(val, VAL); in superio_outb()
122 val = inb(VAL) << 8; in superio_inw()
124 val |= inb(VAL); in superio_inw()
/linux/kernel/locking/
A Dqrwlock.c32 atomic_cond_read_acquire(&lock->cnts, !(VAL & _QW_LOCKED)); in queued_read_lock_slowpath()
48 atomic_cond_read_acquire(&lock->cnts, !(VAL & _QW_LOCKED)); in queued_read_lock_slowpath()
78 cnts = atomic_cond_read_relaxed(&lock->cnts, VAL == _QW_WAITING); in queued_write_lock_slowpath()
A Dqspinlock.c338 (VAL != _Q_PENDING_VAL) || !cnt--); in queued_spin_lock_slowpath()
382 atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_MASK)); in queued_spin_lock_slowpath()
511 val = atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK)); in queued_spin_lock_slowpath()
551 next = smp_cond_load_relaxed(&node->next, (VAL)); in queued_spin_lock_slowpath()
/linux/drivers/staging/rtl8723bs/hal/
A DHalPhyRf_8723B.c19 #define VAL 1 macro
971 …pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_X… in _PHY_PathAFillIQKMatrix8723B()
979 …pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_E… in _PHY_PathAFillIQKMatrix8723B()
987 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; in _PHY_PathAFillIQKMatrix8723B()
1003 …pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_R… in _PHY_PathAFillIQKMatrix8723B()
1049 …pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_X… in _PHY_PathBFillIQKMatrix8723B()
1062 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; in _PHY_PathBFillIQKMatrix8723B()
1094 (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && in ODM_SetIQCbyRFpath()
1095 (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) && in ODM_SetIQCbyRFpath()
1096 (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && in ODM_SetIQCbyRFpath()
[all …]
/linux/tools/testing/selftests/sysctl/
A Dsysctl.sh132 VAL=""
136 VAL="60"
139 VAL="1"
142 VAL="314"
145 VAL="(none)"
148 VAL=""
153 echo -n $VAL > $TARGET
/linux/include/asm-generic/
A Dbarrier.h216 __unqual_scalar_typeof(*ptr) VAL; \
218 VAL = READ_ONCE(*__PTR); \
223 (typeof(*ptr))VAL; \
/linux/drivers/scsi/
A Dsun3x_esp.c45 #define dma_write32(VAL, REG) \
46 writel((VAL), esp->dma_regs + (REG))
50 #define dma_write32(VAL, REG) \ argument
51 do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
A Daha152x.h289 #define SETPORT(PORT, VAL) outb( (VAL), (PORT) ) argument
/linux/drivers/comedi/drivers/
A Ds626.h447 #define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) argument
448 #define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) argument
449 #define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) argument
/linux/include/linux/
A Ddma-mapping.h587 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) argument
589 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) argument
594 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) argument
596 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) argument
/linux/drivers/hwmon/
A Dsmsc47b397.c42 #define VAL 0x2f /* The value to read/write */ macro
47 outb(val, VAL); in superio_outb()
53 return inb(VAL); in superio_inb()
/linux/drivers/net/ethernet/freescale/fs_enet/
A Dmii-fec.c47 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument

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