Searched refs:VCS0 (Results 1 – 16 of 16) sorted by relevance
/linux/drivers/gpu/drm/i915/ |
A D | i915_pci.c | 350 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 360 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 369 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 400 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 451 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 524 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 665 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 889 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 908 BIT(VCS0) | BIT(VCS2), 1022 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | [all …]
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A D | i915_drv.h | 1620 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
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A D | i915_gpu_error.c | 1205 case VCS0: in engine_record_registers()
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A D | i915_irq.c | 4329 intel_engine_cs_irq(dev_priv->gt.engine[VCS0], in i965_irq_handler()
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/linux/drivers/gpu/drm/i915/gt/ |
A D | intel_engine_types.h | 106 VCS0, enumerator 114 #define _VCS(n) (VCS0 + (n))
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A D | intel_engine_user.c | 163 [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS }, in legacy_ring_idx()
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A D | intel_mocs.c | 541 [VCS0] = __GEN9_VCS0_MOCS0, in mocs_offset()
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A D | intel_reset.c | 303 [VCS0] = GEN6_GRDOM_MEDIA, in gen6_reset_engines() 498 [VCS0] = GEN11_GRDOM_MEDIA, in gen11_reset_engines()
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A D | intel_ring_submission.c | 91 case VCS0: in set_hwsp()
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A D | intel_engine_cs.c | 68 [VCS0] = {
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A D | intel_execlists_submission.c | 3362 [VCS0] = GEN8_VCS0_IRQ_SHIFT, in logical_ring_default_irqs()
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/linux/drivers/gpu/drm/i915/gvt/ |
A D | mmio_context.c | 157 [VCS0] = 0xc900, 344 [VCS0] = 0x4264, 401 [VCS0] = 0xc900, in switch_mocs()
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A D | execlist.c | 51 [VCS0] = VCS_AS_CONTEXT_SWITCH,
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A D | cmd_parser.c | 422 #define R_VCS1 BIT(VCS0) 604 [VCS0] = { 1158 [VCS0] = {
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A D | handlers.c | 333 engine_mask |= BIT(VCS0); in gdrst_mmio_write() 2082 id = VCS0; in gvt_reg_tlb_control_handler()
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/linux/drivers/gpu/drm/i915/gem/ |
A D | i915_gem_execbuffer.c | 2306 [I915_EXEC_BSD] = VCS0,
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