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Searched refs:VCS0 (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/i915/
A Di915_pci.c350 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
360 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
369 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
400 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
451 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
524 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
665 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
889 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
908 BIT(VCS0) | BIT(VCS2),
1022 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
[all …]
A Di915_drv.h1620 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
A Di915_gpu_error.c1205 case VCS0: in engine_record_registers()
A Di915_irq.c4329 intel_engine_cs_irq(dev_priv->gt.engine[VCS0], in i965_irq_handler()
/linux/drivers/gpu/drm/i915/gt/
A Dintel_engine_types.h106 VCS0, enumerator
114 #define _VCS(n) (VCS0 + (n))
A Dintel_engine_user.c163 [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS }, in legacy_ring_idx()
A Dintel_mocs.c541 [VCS0] = __GEN9_VCS0_MOCS0, in mocs_offset()
A Dintel_reset.c303 [VCS0] = GEN6_GRDOM_MEDIA, in gen6_reset_engines()
498 [VCS0] = GEN11_GRDOM_MEDIA, in gen11_reset_engines()
A Dintel_ring_submission.c91 case VCS0: in set_hwsp()
A Dintel_engine_cs.c68 [VCS0] = {
A Dintel_execlists_submission.c3362 [VCS0] = GEN8_VCS0_IRQ_SHIFT, in logical_ring_default_irqs()
/linux/drivers/gpu/drm/i915/gvt/
A Dmmio_context.c157 [VCS0] = 0xc900,
344 [VCS0] = 0x4264,
401 [VCS0] = 0xc900, in switch_mocs()
A Dexeclist.c51 [VCS0] = VCS_AS_CONTEXT_SWITCH,
A Dcmd_parser.c422 #define R_VCS1 BIT(VCS0)
604 [VCS0] = {
1158 [VCS0] = {
A Dhandlers.c333 engine_mask |= BIT(VCS0); in gdrst_mmio_write()
2082 id = VCS0; in gvt_reg_tlb_control_handler()
/linux/drivers/gpu/drm/i915/gem/
A Di915_gem_execbuffer.c2306 [I915_EXEC_BSD] = VCS0,

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