Searched refs:VCS1 (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/i915/gvt/ |
| A D | mmio_context.c | 130 {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
158 [VCS1] = 0xca00,
345 [VCS1] = 0x4268,
402 [VCS1] = 0xca00, in switch_mocs()
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| A D | execlist.c | 52 [VCS1] = VCS2_AS_CONTEXT_SWITCH,
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| A D | interrupt.c | 543 if (HAS_ENGINE(gvt->gt, VCS1)) { in gen8_init_irq()
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| A D | cmd_parser.c | 423 #define R_VCS2 BIT(VCS1)
637 [VCS1] = {
1163 [VCS1] = {
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| A D | handlers.c | 345 engine_mask |= BIT(VCS1); in gdrst_mmio_write()
2085 id = VCS1; in gvt_reg_tlb_control_handler()
2164 if (HAS_ENGINE(gvt->gt, VCS1)) \
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| /linux/drivers/gpu/drm/i915/ |
| A D | i915_pci.c | 600 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
665 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
747 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
768 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
1022 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
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| /linux/drivers/gpu/drm/i915/gt/ |
| A D | intel_engine_types.h | 107 VCS1, enumerator
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| A D | intel_mocs.c | 542 [VCS1] = __GEN9_VCS1_MOCS0, in mocs_offset()
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| A D | intel_reset.c | 304 [VCS1] = GEN8_GRDOM_MEDIA2, in gen6_reset_engines()
499 [VCS1] = GEN11_GRDOM_MEDIA2, in gen11_reset_engines()
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| A D | intel_engine_cs.c | 77 [VCS1] = {
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| A D | intel_execlists_submission.c | 3363 [VCS1] = GEN8_VCS1_IRQ_SHIFT, in logical_ring_default_irqs()
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Completed in 36 milliseconds