Searched refs:WREG32_ENDPOINT (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/gpu/drm/radeon/ |
| A D | dce6_afmt.c | 149 WREG32_ENDPOINT(dig->pin->offset, in dce6_afmt_write_latency_fields()
174 WREG32_ENDPOINT(dig->pin->offset, in dce6_afmt_hdmi_write_speaker_allocation()
199 WREG32_ENDPOINT(dig->pin->offset, in dce6_afmt_dp_write_speaker_allocation()
254 WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value); in dce6_afmt_write_sad_regs()
265 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce6_audio_enable()
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| A D | dce3_1_afmt.c | 45 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce3_2_afmt_hdmi_write_speaker_allocation()
63 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce3_2_afmt_dp_write_speaker_allocation()
112 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); in dce3_2_afmt_write_sad_regs()
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| A D | evergreen_hdmi.c | 117 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); in dce4_afmt_write_latency_fields()
135 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce4_afmt_hdmi_write_speaker_allocation()
153 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce4_afmt_dp_write_speaker_allocation()
202 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); in evergreen_hdmi_write_sad_regs()
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| A D | radeon_audio.h | 32 #define WREG32_ENDPOINT(block, reg, v) \ macro
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