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Searched refs:_REG (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/meson/
A Dmeson_viu.c131 _REG(VIU_OSD1_MATRIX_COEF22_30)); in meson_viu_set_osd_matrix()
134 _REG(VIU_OSD1_MATRIX_COEF31_32)); in meson_viu_set_osd_matrix()
142 _REG(VIU_OSD1_MATRIX_COEF22_30)); in meson_viu_set_osd_matrix()
166 _REG(VIU_OSD1_EOTF_CTL + i + 1)); in meson_viu_set_osd_matrix()
204 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
207 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
211 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
215 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
218 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
234 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
[all …]
A Dmeson_crtc.c478 _REG(VD1_IF0_GEN_REG)); in meson_crtc_irq()
481 _REG(VD2_IF0_GEN_REG)); in meson_crtc_irq()
493 _REG(VIU_VD1_FMT_W)); in meson_crtc_irq()
496 _REG(VIU_VD2_FMT_W)); in meson_crtc_irq()
499 _REG(VD1_IF0_CANVAS0)); in meson_crtc_irq()
502 _REG(VD1_IF0_CANVAS1)); in meson_crtc_irq()
505 _REG(VD2_IF0_CANVAS0)); in meson_crtc_irq()
508 _REG(VD2_IF0_CANVAS1)); in meson_crtc_irq()
511 _REG(VD1_IF0_LUMA_X0)); in meson_crtc_irq()
514 _REG(VD1_IF0_LUMA_X1)); in meson_crtc_irq()
[all …]
A Dmeson_venc.c1157 _REG(ENCI_VFIFO2VD_PIXEL_START)) in meson_venc_hdmi_mode_set()
1236 + _REG(ENCI_DVI_VSO_ELINE_EVN)); in meson_venc_hdmi_mode_set()
1239 + _REG(ENCI_DVI_VSO_END_EVN)); in meson_venc_hdmi_mode_set()
1245 + _REG(ENCI_DVI_VSO_ELINE_ODD)); in meson_venc_hdmi_mode_set()
1248 + _REG(ENCI_DVI_VSO_END_ODD)); in meson_venc_hdmi_mode_set()
1285 + _REG(ENCI_DVI_VSO_BEGIN_EVN)); in meson_venc_hdmi_mode_set()
1293 + _REG(ENCI_DVI_VSO_ELINE_ODD)); in meson_venc_hdmi_mode_set()
1296 + _REG(ENCI_DVI_VSO_END_ODD)); in meson_venc_hdmi_mode_set()
1301 + _REG(ENCI_DVI_VSO_ELINE_EVN)); in meson_venc_hdmi_mode_set()
1304 + _REG(ENCI_DVI_VSO_END_EVN)); in meson_venc_hdmi_mode_set()
[all …]
A Dmeson_vpp.c63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
112 priv->io_base + _REG(VPP_OFIFO_SIZE)); in meson_vpp_init()
119 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
123 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
129 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
146 priv->io_base + _REG(VPP_SC_MISC)); in meson_vpp_init()
[all …]
A Dmeson_osd_afbcd.c90 priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
91 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
100 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_enable()
108 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_disable()
134 priv->io_base + _REG(OSD1_AFBCD_SIZE_IN)); in meson_gxm_afbcd_setup()
137 priv->io_base + _REG(OSD1_AFBCD_HDR_PTR)); in meson_gxm_afbcd_setup()
139 priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR)); in meson_gxm_afbcd_setup()
142 priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR)); in meson_gxm_afbcd_setup()
158 priv->io_base + _REG(OSD1_AFBCD_CONV_CTRL)); in meson_gxm_afbcd_setup()
284 priv->io_base + _REG(MALI_AFBCD_TOP_CTRL)); in meson_g12a_afbcd_init()
[all …]
A Dmeson_rdma.c39 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
43 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
68 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_setup()
75 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_stop()
81 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_stop()
113 writel_relaxed(val, priv->io_base + _REG(reg)); in meson_rdma_writel_sync()
122 priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); in meson_rdma_flush()
126 priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); in meson_rdma_flush()
132 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_flush()
A Dmeson_dw_hdmi.c434 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
509 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
515 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
517 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
527 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
532 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
535 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
771 priv->io_base + _REG(VPU_HDMI_SETTING)); in meson_venc_hdmi_encoder_disable()
773 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_encoder_disable()
774 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_encoder_disable()
[all …]
A Dmeson_drv.c72 (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG)); in meson_irq()
140 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); in meson_vpu_init()
144 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); in meson_vpu_init()
149 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); in meson_vpu_init()
153 writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); in meson_vpu_init()
A Dmeson_overlay.c736 writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); in meson_overlay_atomic_disable()
737 writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); in meson_overlay_atomic_disable()
738 writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0)); in meson_overlay_atomic_disable()
739 writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0)); in meson_overlay_atomic_disable()
742 priv->io_base + _REG(VPP_MISC)); in meson_overlay_atomic_disable()
A Dmeson_plane.c175 _REG(VIU_OSD1_CTRL_STAT2)); in meson_plane_atomic_update()
412 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); in meson_plane_atomic_disable()
415 priv->io_base + _REG(VPP_MISC)); in meson_plane_atomic_disable()
A Dmeson_venc_cvbs.c186 priv->io_base + _REG(VENC_VDAC_DACSEL0)); in meson_venc_cvbs_encoder_enable()
A Dmeson_registers.h12 #define _REG(reg) ((reg) << 2) macro
/linux/sound/soc/qcom/
A Dlpass-lpaif-reg.h134 LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
135 LPAIF_RDMA##reg##_REG(v, chan))
140 LPAIF_WRDMA##reg##_REG(v, chan))
/linux/drivers/iommu/intel/
A Ddebugfs.c39 { DMAR_##_reg_##_REG, __stringify(_reg_) }

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