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Searched refs:__REG (Results 1 – 14 of 14) sorted by relevance

/linux/arch/arm/mach-pxa/
A Dpxa27x-udc.h9 #define UDCCR __REG(0x40600000) /* UDC Control Register */
179 #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
180 #define UDCDRA __REG(0x40600304) /* Data Register - EPA */
181 #define UDCDRB __REG(0x40600308) /* Data Register - EPB */
182 #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
183 #define UDCDRD __REG(0x40600310) /* Data Register - EPD */
184 #define UDCDRE __REG(0x40600314) /* Data Register - EPE */
185 #define UDCDRF __REG(0x40600318) /* Data Register - EPF */
186 #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
187 #define UDCDRH __REG(0x40600320) /* Data Register - EPH */
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A Dregs-rtc.h11 #define RCNR __REG(0x40900000) /* RTC Count Register */
12 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
13 #define RTSR __REG(0x40900008) /* RTC Status Register */
14 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
15 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
A Dpxa27x.h11 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
/linux/arch/arm/mach-pxa/include/mach/
A Dregs-uart.h11 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
12 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
14 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
15 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
16 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
17 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
18 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
19 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
20 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
34 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
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A Dpxa2xx-regs.h41 #define PCMD0 __REG(0x40F00080 + 0 * 4)
42 #define PCMD1 __REG(0x40F00080 + 1 * 4)
43 #define PCMD2 __REG(0x40F00080 + 2 * 4)
44 #define PCMD3 __REG(0x40F00080 + 3 * 4)
45 #define PCMD4 __REG(0x40F00080 + 4 * 4)
46 #define PCMD5 __REG(0x40F00080 + 5 * 4)
47 #define PCMD6 __REG(0x40F00080 + 6 * 4)
48 #define PCMD7 __REG(0x40F00080 + 7 * 4)
49 #define PCMD8 __REG(0x40F00080 + 8 * 4)
50 #define PCMD9 __REG(0x40F00080 + 9 * 4)
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A Dpxa3xx-regs.h26 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */
27 #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
28 #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
30 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
31 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
33 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
35 #define PCMD(x) __REG(0x40F50110 + ((x) << 2))
41 #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
129 #define CKENA __REG(0x4134000C) /* A Clock Enable Register */
130 #define CKENB __REG(0x41340010) /* B Clock Enable Register */
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A Dregs-ac97.h11 #define POCR __REG(0x40500000) /* PCM Out Control Register */
15 #define PICR __REG(0x40500004) /* PCM In Control Register */
19 #define MCCR __REG(0x40500008) /* Mic In Control Register */
23 #define GCR __REG(0x4050000C) /* Global Control Register */
39 #define POSR __REG(0x40500010) /* PCM Out Status Register */
43 #define PISR __REG(0x40500014) /* PCM In Status Register */
48 #define MCSR __REG(0x40500018) /* Mic In Status Register */
53 #define GSR __REG(0x4050001C) /* Global Status Register */
72 #define CAR __REG(0x40500020) /* CODEC Access Register */
75 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
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A Dhardware.h40 # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) macro
45 (*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))
51 # define __REG(x) io_p2v(x) macro
/linux/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_main_regs.h54 #define __REG(...) __VA_ARGS__ macro
57 #define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC, 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4)
546 #define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 0, 0, 1, 4)
549 #define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 4, 0, 1, 4)
552 #define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 8, 0, 1, 4)
2193 #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\
2197 #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\
2444 #define DSM_RAM_INIT __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
3110 #define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
4244 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
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/linux/arch/arm/mach-sa1100/include/mach/
A DSA-1100.h884 #define PMCR __REG(0x90020000) /* PM Control Reg. */
885 #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */
886 #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
887 #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
1025 #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */
1026 #define RCSR __REG(0x90030004) /* RC Status Reg. */
1043 #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */
1369 #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */
1370 #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */
1371 #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */
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A Dhardware.h44 # define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x))) macro
49 # define __REG(x) io_p2v(x) macro
/linux/drivers/phy/microchip/
A Dsparx5_serdes_regs.h29 #define __REG(...) __VA_ARGS__ macro
32 #define SD10G_LANE_LANE_01(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4)
53 #define SD10G_LANE_LANE_02(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4)
86 #define SD10G_LANE_LANE_03(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4)
95 #define SD10G_LANE_LANE_04(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4)
104 #define SD10G_LANE_LANE_06(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4)
2111 #define SD_CMU_CMU_00(t) __REG(TARGET_SD_CMU, t, 14, 0, 0, 1, 20, 0, 0, 1, 4)
2363 #define SD_LANE_SD_SER_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 0, 0, 1, 4)
2372 #define SD_LANE_SD_DES_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 4, 0, 1, 4)
2381 #define SD_LANE_SD_LANE_CFG(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 0, 0, 1, 4)
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/linux/sound/soc/pxa/
A Dpxa2xx-i2s.c32 #define SACR0 __REG(0x40400000) /* Global Control Register */
33 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
34 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Reg…
35 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
36 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
37 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
38 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
/linux/arch/xtensa/include/asm/
A Dcoprocessor.h102 __REG ## list (cc, abi, type, name, size, align)

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